DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on September 12, 2024 has been fully considered by the examiner.
Specification
3. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Storage Device Using a Multi-Stage Read with Floating Word Line”
4. The disclosure is objected to because of the following informalities.
¶[0084] recites “A latch circuit SLC includes n-type MOSFETs 48 and 49, and inverter circuits 50 and 51.” This appears to reference FIG. 7, latch circuit SDL. Therefore, Examiner believes ¶[0084] should recite, “A latch circuit [[SLC]] SDL includes n-type MOSFETs 48 and 49, and inverter circuits 50 and 51.”
Appropriate correction is required.
Claim Rejections - 35 USC § 112
5. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
6. Claims 14-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 14 recites in lines 2-4, “a plurality of N memory cell transistors,” “a plurality of N bit lines,” and “a plurality of N sense amplifiers,” respectively. The meanings of these limitations are indefinite. It is unclear if each limitation refers to a plurality of sets of N elements (e.g., a plurality of word lines, each word line having N memory cell transistors) or if “plurality” is synonymous with N (i.e., N memory cell transistors is the plurality in view, in which case “plurality” and “N” are redundant). Claims 15-20 depend on claim 14.
Because “word line” is singular in the claim, for this purpose of this action:
“a plurality of N memory cell transistors, where N is an integer greater than 1” shall be interpreted as “ N memory cell transistors, where N is an integer greater than 1”;
“a plurality of N bit lines respectively connected to the memory cell transistors” shall be interpreted as “ N bit lines respectively connected to the memory cell transistors”; and
“a plurality of N sense amplifier units respectively connected to the bit lines” shall be interpreted as “ N sense amplifier units respectively connected to the N bit lines.”
Claim 14 recites the limitation “the bit lines” in line 4. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, “the bit lines” in line 4 shall be interpreted as “the N bit lines,” which finds antecedent basis in line 3.
Claim 14 recites the limitation “the N memory cell transistors” in line 5. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the apparent antecedent “a plurality of the N memory cell transistors” in line 2 shall be interpreted as “ N memory cell transistors,” so that it provides antecedent basis for “the N memory cell transistors” in line 5.
Claim 14 recites the limitation “supplying a first voltage to the word line” in line 10, which is indefinite. For the purpose of this action, “supplying a first voltage to the word line” in line 10 shall be interpreted as “supplying [[a]] the first voltage to the word line,” which finds antecedent basis in line 6.
Claim 14 recites the limitation “N-bit first data based on N first currents respectively flowing to the bit lines” in lines 10-11, and “N-bit second data based on N second currents respectively flowing to the bit lines” in lines 13-14. These meanings of these limitations are indefinite in light of the specification.
In order for the number of bits (N) in the first and second data to equal the number of bit lines (also N), the scope of the claim must be limited to memory cells configured to store only one bit each (e.g., single-level cells). However, the drawings (e.g., FIG. 4) and specification (e.g., ¶[0054-0056]) clearly have multiple bits per cell in view, with three bits per cell exemplified. Note that 3 bits per cell would represent 3N first data bits based on N first currents, for example.
For this purpose of this action, the limitation “N-bit first data based on N first currents respectively flowing to the bit lines” in lines 10-11 shall be interpreted as “[[N-bit]] first data based on N first currents respectively flowing to the bit lines” in lines 10-11, and “N-bit second data based on N second currents respectively flowing to the bit lines” in lines 13-14 shall be interpreted as “[[N-bit]] second data based on N second currents respectively flowing to the bit lines.”
Claim 15 recites the limitation “generate N-bit third data based on the N-bit first data and the N-bit second data, and first state data based on the N-bit third data is output” in lines 2-3. These meanings of these limitations are indefinite in light of the specification (see the explanation with respect to claim 14 preceding). For the purpose of this action, the limitation “N-bit third data” in lines 2-3 shall be interpreted as “[[N-bit]] third data.”
Claim 16 recites the limitation “the first bit to the i-th bit of the N-bit first data are respectively based on respective threshold voltages of the N memory cell transistors, and
the first bit to the i-th bit of the N-bit second data are respectively based on the respective threshold voltages of the N memory cell transistors” in lines 2-5. These meanings of these limitations are indefinite.
It is unclear what the “i-th bit” refers to or what the significance of “i” is. Also, if the first bit to the i-th bits of the first and second data are respectively based on the respective threshold voltages of the N memory cell transistors, it is then unclear what the (i+1)th to Nth bits are based on.
Claims 17 and 18 each recite the limitation “a programming operation to raise a threshold voltage of the memory cell transistors is repeated several times” in lines 2-3. There is insufficient antecedent basis for this limitation in the claim. For the purpose of this action, the limitation “a programming operation to raise a threshold voltage of the memory cell transistors is repeated several times” shall be interpreted as “a programming operation to raise a threshold voltage of [[the]] a memory cell transistor of the N memory cell transistors is repeated several times” (see also preceding comments on “N memory cell transistors” with respect to claim 14).
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
8. Claims 1-2, 5-7, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Guliani, et al (US 20160217853 A1), hereinafter Guliani.
Regarding independent claim 1, Guliani teaches a semiconductor storage device (FIG. 1, 110) comprising:
a memory cell transistor (FIG. 1, cells of array 140);
a bit line connected to the memory cell transistor (FIG. 1, BL[0]..BL[M-1]);
a sense amplifier unit connected to the bit line (FIG. 1, 142);
a word line connected to the memory cell transistor (FIG. 1, WL[0]..WL[N-1]); and
a control circuit connected to the sense amplifier unit and configured to execute a first operation (¶[0020] teaches “the control logic performs the read by selecting the local wordline driver and the global wordline driver to connect the selected memory cell to the sensing circuit”), wherein
the first operation includes
during a first period, supplying a first voltage to the word line and acquiring first data based on a first current flowing to the bit line (¶[0021] teaches “the first stage of the multistage read can be a no-float read, also known as pseudo-static read,” meaning a voltage is applied; claim 21 teaches “a sensing circuit to read the memory cell when current flows through the memory cell”), and
during a second period following the first period, placing the word line in an electrically floating state and acquiring second data based on a second current flowing to the bit line (¶[0021] teaches “If a first stage is a no-float read, there can be a three stage read by then floating the global wordline in a second stage and floating the local wordline in a third stage, for example”; claim 21).
Regarding claim 2, Guliani teaches the limitations of claim 1.
Guliani further teaches the first data and the second data are based on a threshold voltage of the memory cell transistor (¶[0023]).
Regarding claim 5, Guliani teaches the limitations of claim 1.
Guliani further teaches a driver (¶[0014]) configured to apply the first voltage to the word line (e.g., the “initial voltage” of ¶[0021]).
Regarding claim 6, Guliani teaches the limitations of claim 5.
Guliani further teaches the word line is placed in the electrically floating state by disconnecting the word line from the driver (¶[0020] teaches “the control logic floats the local wordline by deselecting the local wordline driver”; FIG. 4, when select signal LWLSEL deselects the local word line driver, the local word line is disconnected from the global word line GWL; ¶[0058]).
Regarding claim 7, Guliani teaches the limitations of claim 5.
Guliani further teaches the word line is placed in the electrically floating state by disabling the driver (¶[0040] teaches “the control logic disables the global wordline driver by deselecting the global wordline select signal 220” and ” When the global wordline driver is disabled and the local wordline driver is still enabled, the wordline is considered to be floating”).
Regarding claim 13, Guliani teaches the limitations of claim 1.
Guliani further teaches the control circuit is configured to perform the first operation in response to a command to perform the first operation received independently of a command to perform a write operation (¶[0059] teaches “the processor generates a memory access command…The access command can be a read command”).
Claim Rejections - 35 USC § 103
9. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
10. Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Guliani, et al (US 20160217853 A1), hereinafter Guliani, in view of Dutta, et al (US 20130070524 A1), hereinafter Dutta.
Regarding claim 3, Guliani teaches the limitations of claim 1.
Guliani does not teach the control circuit is configured to generate third data based on the first data and the second data, and first state data based on the third data is output to an external memory controller when a first command is received from the memory controller.
Dutta teaches the control circuit (FIG. 3, 220) is configured to generate third data (e.g., FIG. 10A, result of comparison in step 1012) based on the first data (FIG. 10A, 1002, 1004) and the second data (FIG. 10A, 1008, 1010) and first state data (result of comparison in step 1014) based on the third data (“third data” from step 1012 is input to step 1014) is output to an external memory controller (FIG. 3, controller 244 is external to memory die 212; ¶[0096] teaches the result of the process of FIG. 10A may impact ECC processing on controller 244) when a first command is received from the memory controller (¶[0045] teaches commands are transferred between controller 244 and one or more memory dies via lines 234; ¶[0047] teaches controller 244 is a “managing circuit”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dutta into the method of Guliani to include comparing first and second read data. The ordinary artisan would have been motivated to modify Guliani in the above manner for the purpose of determining if the number of mis-compares is within the error correction capabilities of the controller (Dutta ¶[0089]).
Regarding claim 4, Guliani teaches the limitations of claim 3.
Dutta further teaches the third data has a first value when the first data and the second data are different, and has a second value when the first data and the second data are same (¶[0088] teaches “if the read results for a given memory cell were the same for the two reads, then the comparison produces a ‘0,’ in this embodiment. However, if the read results for a given memory cell were different for the two reads, then the comparison produces a ‘1’”).
11. Claims 8-12 are rejected under 35 U.S.C. 103 as being unpatentable over Guliani, et al (US 20160217853 A1), hereinafter Guliani, in view of Chen (US 20070153594 A1).
Regarding claim 8, Guliani teaches the limitations of claim 5.
Guliani further teaches a second memory cell transistor connected between the memory cell transistor and the bit line (e.g., in FIG. 1, if “the word line” is WL[0] and “the memory cell transistor” is coupled to WL[0] and BL[0], a “second memory cell transistor” may be coupled to WL[1] and BL[0] and therefore be between “the memory cell transistor” and “the bit line”); and
a second word line (FIG. 1, e.g., WL[1]) connected to the second memory cell transistor (e.g., transistor coupled to WL[1} and BL[0]), wherein
the driver is also connected to the second word line (the present application teaches in FIG. 5 and ¶[0065] “driver” 17 includes “drivers” CGD0..7; Guliani teaches in FIG. 4, the “driver” includes multiple local word line drivers, shown coupled to the two illustrated word lines, and so teaches the “driver” is also connected to the second word line).
Guliani does not teach the driver supplies a second voltage higher than the first voltage to the second word line during the first period and the second period.
Chen teaches the driver supplies a second voltage higher than the first voltage to the second word line during the first period and the second period (¶[0046] teaches “In the read and verify operations…the unselected word lines…of the selected block are raised to a read pass voltage”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Chen into the method of Guliani to include applying pass voltages to unselected word lines in read and verify operations. The ordinary artisan would have been motivated to modify Guliani in the above manner for the purpose of making the transistors operate as pass gates (Chen ¶[0046]).
Regarding claim 9, Guliani teaches the limitations of claim 1.
Guliani does not teach the control circuit is configured to perform the first operation during a time period in which a programming operation to raise a threshold voltage of the memory cell transistor is repeated multiple times in response to a command to perform a write operation.
Chen teaches the control circuit is configured to perform the first operation during a time period in which a programming operation to raise a threshold voltage of the memory cell transistor is repeated multiple times in response to a command to perform a write operation (FIG. 13, 502; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) and raises a threshold voltage via a repeated process (see steps 524, 528)).
Regarding claim 10, Guliani teaches the limitations of claim 1.
Guliani does not teach the control circuit is configured to perform the first operation after a time period in which a programming operation to raise a threshold voltage of the memory cell transistor is repeated multiple times in response to a command to perform a write operation.
Chen teaches the control circuit is configured to perform the first operation after a time period in which a programming operation to raise a threshold voltage of the memory cell transistor is repeated multiple times in response to a command to perform a write operation (FIG. 13; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) and raises a threshold voltage via a repeated process (see steps 524, 528)).
Regarding claim 11, Guliani teaches the limitations of claim 1.
Guliani does not teach the control circuit is configured to perform the first operation each time a write operation is performed.
Chen teaches the control circuit is configured to perform the first operation each time a write operation is performed (FIG. 13 shows a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) is executed in each iteration of a write operation).
Regarding claim 12, Guliani teaches the limitations of claim 1.
Guliani does not teach the control circuit is configured to perform the first operation in response to a command set that includes a command to perform a write operation and a command to perform the first operation.
Chen teaches the control circuit is configured to perform the first operation in response to a command set that includes a command to perform a write operation and a command to perform the first operation (FIG. 13, 502; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”)).
Regarding claims 9-12, because both the “first operation” of Guliani and the verify operation of Chen utilize a non-floating word line read operation, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the read operation of Guliani with the read portion of the verify operation of Chen to yield predictable results. See MPEP § 2143(I)(B).
12. Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Guliani, et al (US 20160217853 A1), hereinafter Guliani, in view of Lee (US 20240177791 A1).
Regarding independent claim 14, Guliani teaches a semiconductor storage device (FIG. 1, 110) comprising:
a plurality of N memory cell transistors, where N is an integer greater than 1 (FIG. 1, plurality of cells of array 140);
a plurality of N bit lines respectively connected to the memory cell transistors (FIG. 1, BL[0]..BL[M-1]);
a plurality of N sense amplifier units (FIG. 1, 142) respectively connected to the bit lines (FIG. 1, BL[0]..BL[M-1]);
a word line connected to the N memory cell transistors in common (FIG. 1, WL[0]..WL[N-1], each of which may be connected to a row of memory cell transistors in common);
a driver (¶[0014]) configured to supply a first voltage to the word line (e.g., the “initial voltage” of ¶[0021]); and
a control circuit connected to the sense amplifier units and the driver and configured to execute a first operation (¶[0020] teaches “the control logic performs the read by selecting the local wordline driver and the global wordline driver to connect the selected memory cell to the sensing circuit”), wherein
the first operation includes
during a first period, supplying a first voltage to the word line and acquiring N-bit first data based on N first currents respectively flowing to the bit lines (¶[0021] teaches “the first stage of the multistage read can be a no-float read, also known as pseudo-static read,” meaning a voltage is applied; claim 21 teaches “a sensing circuit to read the memory cell when current flows through the memory cell”), and
during a second period following the first period, placing the word line in an electrically floating state, and acquiring N-bit second data based on N second currents respectively flowing to the bit lines (¶[0021] teaches “If a first stage is a no-float read, there can be a three stage read by then floating the global wordline in a second stage and floating the local wordline in a third stage, for example”; claim 21).
Guliani does not teach the same number of sensing units (N) as bit lines.
Lee teaches the same number of sensing units (N) as bit lines (FIG. 1 shows one page buffer (PB1..PBm) per bit line (BL1..BLm); FIG. 3 shows each page buffer circuit contains a sense amplifier; ¶[0057-0062]).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Lee into the method of Guliani to include a page buffer for each bit line. The ordinary artisan would have been motivated to modify Guliani in the above manner for the purpose of each of the page buffers PB1 to PBm sensing, through a sensing node, a change in the amount of flowing current depending on the program state of the corresponding memory cell and latch the sensed change as sensing data while continuously supplying a sensing current to the bit lines coupled to the memory cells (Lee ¶[0035]).
13. Claims 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Guliani, et al (US 20160217853 A1), hereinafter Guliani, in view of Lee (US 20240177791 A1), and further in view of Dutta, et al (US 20130070524 A1), hereinafter Dutta.
Regarding claim 15, Guliani as modified by Lee teaches the limitations of claim 14.
Guliani does not teach the control circuit is configured to generate N-bit third data based on the N-bit first data and the N-bit second data, and first state data based on the N-bit third data is output to an external memory controller when a first command is received from the memory controller.
Dutta teaches the control circuit (FIG. 3, 220) is configured to generate N-bit third data (e.g., FIG. 10A, result of comparison in step 1012) based on the N-bit first data (FIG. 10A, 1002, 1004) and the N-bit second data (FIG. 10A, 1008, 1010), and first state data (result of comparison in step 1014) based on the N-bit third data (“third data” from step 1012 is input to step 1014) is output to an external memory controller (FIG. 3, controller 244 is external to memory die 212; ¶[0096] teaches the result of the process of FIG. 10A may impact ECC processing on controller 244) when a first command is received from the memory controller (¶[0045] teaches commands are transferred between controller 244 and one or more memory dies via lines 234; ¶[0047] teaches controller 244 is a “managing circuit”).
It would have been obvious to one of ordinary skill of the art before the time of the effective filing date of the invention to incorporate the teachings of Dutta into the method of Guliani to include comparing first and second read data. The ordinary artisan would have been motivated to modify Guliani in the above manner for the purpose of determining if the number of mis-compares is within the error correction capabilities of the controller (Dutta ¶[0089]).
Regarding claim 16, Guliani as modified by Lee and Dutta teaches the limitations of claim 15.
Guliani further teaches the first bit to the i-th bit of the N-bit first data are respectively based on respective threshold voltages of the N memory cell transistors (¶[0023]), and
the first bit to the i-th bit of the N-bit second data are respectively based on the respective threshold voltages of the N memory cell transistors (¶[0023]).
14. Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Guliani, et al (US 20160217853 A1), hereinafter Guliani, in view of Lee (US 20240177791 A1), and further in view of Chen (US 20070153594 A1).
Regarding claim 17, Guliani as modified by Lee teaches the limitations of claim 14.
Guliani does not teach the control circuit is configured to perform the first operation during a time period in which a programming operation to raise a threshold voltage of the memory cell transistors is repeated multiple times in response to a command to perform a write operation.
Chen teaches the control circuit is configured to perform the first operation during a time period in which a programming operation to raise a threshold voltage of the memory cell transistors is repeated multiple times in response to a command to perform a write operation (FIG. 13, 502; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) ”) and raises a threshold voltage via a repeated process (see steps 524, 528)).
Regarding claim 18, Guliani as modified by Lee teaches the limitations of claim 14.
Guliani does not teach the control circuit is configured to perform the first operation after a time period in which a programming operation to raise a threshold voltage of the memory cell transistors is repeated multiple times in response to a command to perform a write operation.
Chen teaches the control circuit is configured to perform the first operation after a time period in which a programming operation to raise a threshold voltage of the memory cell transistors is repeated multiple times in response to a command to perform a write operation (FIG. 13; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) and raises a threshold voltage via a repeated process (see steps 524, 528)).
Regarding claim 19, Guliani as modified by Lee teaches the limitations of claim 14.
Guliani does not teach the control circuit is configured to perform the first operation each time a write operation is performed.
Chen teaches the control circuit is configured to perform the first operation each time a write operation is performed (FIG. 13 shows a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”) is executed in each iteration of a write operation).
Regarding claim 20, Guliani as modified by Lee teaches the limitations of claim 14.
Guliani does not teach the control circuit is configured to perform the first operation in response to a command set that includes a command to perform a write operation and a command to perform the first operation.
Chen teaches the control circuit is configured to perform the first operation in response to a command set that includes a command to perform a write operation and a command to perform the first operation (FIG. 13, 502; ¶[0072] teaches the system “receives commands and data to program the memory,” which includes a multi-stage program verify operation (508, 510) using a non-floating word line read (“first operation”)).
Regarding claims 17-20, because both the “first operation” of Guliani and the verify operation of Chen utilize a non-floating word line read operation, it would have been obvious to one of ordinary skill in the art at the time of the invention to substitute the read operation of Guliani with read portion of the verify operation of Chen to yield predictable results. See MPEP § 2143(I)(B).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY COON whose telephone number is (571)270-0740. The examiner can normally be reached M-F 8am-5pm (Eastern).
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/B.S.C./Examiner, Art Unit 2827
/AMIR ZARABIAN/ Supervisory Patent Examiner, Art Unit 2827
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