Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on June 9th, 2026, has been received. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Rejections
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
In the event the determination of the status of the application as subject to AIA 35
U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claims 1 – 4 and 6 – 10 are rejected under 35 U.S.C. 103 as being unpatentable over Kawabata et al. (US 20050218441 A1), and further in view of Iwamoto et al. (US 20070210414 A1) and Li (US 20220246625 A1).
Regarding dependent claim 1, Kawabata (US 20050218441 A1) teaches a semiconductor device, comprising:
…
a doped structure (Fig. 2B; second conductive layer 31 + a third conductive layer 33 considered to be a doped structure. See [0021]), … and extending along a second direction vertical to the first direction (Fig. 2B; second conductive layer 31 extending vertically);
a second dielectric layer (Figs. 2A – 2B; element isolating film 32), extending along the first direction and disposed above the doped structure (Figs. 2A – 2B); and
two doped portions (Fig. 2B; straps 35 & [0022]), adjacent to two lateral surfaces of the doped structure (Fig. 2B), …
However, Kawabata remains silent regarding the semiconductor device including:
a fuse metal;
a first dielectric layer, extending along a first direction and disposed above the fuse metal, wherein the first dielectric layer comprises a first recess structure for accommodating the fuse metal; …
the doped structure … formed above the first dielectric layer …
wherein the doped portions are spaced apart from the first dielectric layer and the second dielectric layer.
However, in the same field of endeavor, Iwamoto (US 20070210414 A1) teaches a semiconductor device at least including:
a fuse metal (Fig. 13; metal cap film 9 & [0097]);
a first dielectric layer (Fig. 13; insulator layer 4, including insulator 4b wherein examiner is considering insulator 4b as a first dielectric layer), extending along a first direction (Fig. 13; horizontal direction) and disposed above the fuse metal (Fig. 13), wherein the first dielectric layer comprises a first recess structure for accommodating the fuse metal (Fig. 13; recess accommodating metal cap film 9) …
Examiner asserts that one of ordinary skill in the art would recognize the well-established (within the field of endeavor) function and value of a fuse/effuse structure in the circuit levels layers (e.g., including but not limited to, back end of line (BEOL) or middle of line (MOL) layers). See at least [0003] of Iwamoto. This addition of Iwamoto structure to the semiconductor device of Kawabata yields the semiconductor structure wherein the doped structure is formed above the first dielectric layer & wherein the doped portions are spaced apart from the first dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Kawabata to include Iwamoto’s fuse/efuse structure 10 with associated insulator layer 4 (which is shaped specifically for Iwamoto’s fuse/efuse structure 10), because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, Kawabata’s semiconductor device as modified by Iwamoto’s fuse/efuse structure 10 with associated insulator layer 4 can yield a predictable result of adding the known functions of an efuse, e.g., repair and/or managing device “health”/integrity since fuses are designed to blowout to when a programmed criteria is met within the device. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify Kawabata’s semiconductor device to include Iwamoto’s efuse structure in a way that is similar to Kawabata’s capacitor structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Iwamoto’s substrate , including their efuse structure, is comparable to Kawabata’s substrate, including semiconductor structures, because they are both designed to include semiconductor structures, e.g., efuses. Therefore, it is within the capabilities of one of ordinary skill in the art to modify Kawabata’s semiconductor device to include Iwamoto’s efuse structure in a way that is similar to Kawabata’s capacitor structure with the predictable result of adding the known functions of an efuse to the semiconductor device of Kawabata.
Further, in the same field of endeavor, Li (US 20220246625 A1) teaches a capping layer 126 (Figs. 2G – 3; capping layer 126) over an efuse (i.e., a fuse) region 20 ([0031] & [0041]). Li’s structure shows a conductive structure (considered analogous to the instant doped structure for its ability to conduct current, i.e., for its same function) which traverses the vertical boundary between Li’s second insulating layer 130 (analogous to Kawabata’s interlayer dielectric film 42) and substrate 102; such that capping layer 126, i.e., a second dielectric layer, is separated from the vertical boundary between Li’s second insulating layer 130 and substrate 102. Modifying Kawabata’s doped structure to interconnect between device layers in a way taught by Li yields the semiconductor device structure wherein the doped portions are spaced apart from … the second dielectric layer. Therefore, Kawabata, further in view of Iwamoto and Li, yields the semiconductor device structure wherein the doped portions are spaced apart from the first dielectric layer and the second dielectric layer.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include Li’s teaching of a doped structure traversing semiconductor layers, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Li’s conductive structure is comparable to the doped structure of Kawabata because they serve the same purpose and function. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include Li’s teaching of a doped structure traversing semiconductor layers, with the predictable result of providing isolation for doped layers/regions/portions and connecting upper wiring to the efuse circuit.
Regarding dependent claim 2, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 1, wherein
a distance between the doped portions and the second dielectric layer is less than that of the doped portions and the first dielectric layer (Kawabata Fig. 2A – 2B).
Regarding dependent claim 3, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 1, wherein
the first dielectric layer and the second dielectric layer are in direct contact with the doped structure (yielded through the combination of Kawabata’s second dielectric layer and doped structure, further in view Iwamoto’s first dielectric layer and Li’s second dielectric layer).
Regarding dependent claim 4, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 1; however, Kawabata remains silent on the semiconductor device further comprising:
a first metal structure, disposed below the fuse metal and the first dielectric layer, wherein the fuse metal is surrounded by the first metal structure and the first dielectric layer.
However, in the same field of endeavor, Iwamoto teaches a first metal structure (Fig. 13; main wiring 1), disposed below the fuse metal (Fig. 13) and the first dielectric layer (Fig. 13), wherein the fuse metal is surrounded by the first metal structure (Fig. 13) and the first dielectric layer (Fig. 13). This structure would be obvious in the combination of Kawabata, further in view of Iwamoto, as the inclusion of Iwamoto’s metal cap film 9 would at least include the fuse structure taught by Iwamoto in Fig. 13.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include the components, e.g., main wiring 1 and barrier film 3, of Iwamoto’s efuse structure (Fig. 13), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Iwamoto’s substrate , including their efuse structure, is comparable to Kawabata’s substrate, including semiconductor structures, because they are both designed to include semiconductor structures, e.g., efuses. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include the components, e.g., main wiring 1 and barrier film 3, of Iwamoto’s efuse structure (Fig. 13), with the predictable result of forming an efuse.
Regarding dependent claim 6, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 1, further comprising:
two insulating structures (Kawabata: Figs. 6 – 12; insulating film 30), extending along the second direction (Kawabata: Fig. 11) and contacting the lateral surfaces of the doped structure (Kawabata: Fig. 12), wherein the insulating structures are formed between the doped portions and the first dielectric layer along the second direction (Yield through the combination of Kawabata, further in vier of Iwamoto’s first dielectric layer).
Regarding dependent claim 7, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 6, wherein
the insulating structures are spaced apart from the first dielectric layer and the second dielectric layer.
As discussed above, Kawabata as modified by Iwamoto teach features of the instant semiconductor device as detailed in claims 1 and 6. Kawabata’s device modified by the inclusion of Iwamoto’s metal cap film 9 and insulator layer 4, which ALSO includes insulator layer 4b with insulator layer 4a (see rejection of claim 1). Thus, the inclusion of Iwamoto’s insulating layer 4 to the semiconductor device of Kawabata, further in view of Iwamoto insulating layer 4 and Li’s second dielectric layer, yields the device structure wherein the insulating structures are spaced apart from the first dielectric layer (at least by Iwamoto’s insulating insulator layer 4a) and the second dielectric layer (yield through the modification of the doped structure and second dielectric layer as contributed from Li).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include the components, e.g., main wiring 1 and barrier film 3, of Iwamoto’s efuse structure (Fig. 13), because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Iwamoto’s substrate , including their efuse structure, is comparable to Kawabata’s substrate, including semiconductor structures, because they are both designed to include semiconductor structures, e.g., efuses. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the semiconductor device of Kawabata, further in view of Iwamoto, to include the components, e.g., main wiring 1 and barrier film 3, of Iwamoto’s efuse structure (Fig. 13), with the predictable result of forming an efuse.
Regarding dependent claim 8, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 6, further comprising:
a well region (Kawabata: Figs. 1 and 2B; active area AAb), extending along the first direction (Kawabata: Fig. 1), wherein the insulating structures are formed between the doped structure and the well region (Kawabata: Fig. 2B); and
a doped layer (Kawabata: Figs. 1 – 2B; impurity region 60), extending along the first direction (Kawabata: Figs. 1 – 2B) and disposed on the well region (Kawabata: Figs. 1 – 2B), wherein the doped structure is surrounded by the insulating structures and the doped layer (Kawabata: Figs. 1 – 2B).
Regarding dependent claim 9, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 8, wherein
the doped portions are surrounded by the doped layer (Kawabata: Figs. 1 – 2B), the insulating structures (Kawabata: Figs. 1 – 2B), the doped structure (Kawabata: Figs. 1 – 2B) and the well region (Kawabata: Figs. 1 – 2B).
Regarding dependent claim 10, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 9, wherein
size of each of the doped portions is less than one fifth of thickness of the doped layer (See excerpt of Kawabata’s Fig. 2B below).
PNG
media_image1.png
370
396
media_image1.png
Greyscale
Kawabata shows in Fig. 2B that the strap 35 and the impurity region 60 have a relative relationship of 0.09 : 0.47 (≈ 19% or ≈ one fifth) for their widths.
Therefore, the claimed size of each of the doped portions is less than one fifth of thickness of the doped layer would have been obvious, from at least Fig. 2B of Kawabata, to one of ordinary skill in the art before the effective filing date of the invention because absent evidence or disclosure of criticality for the range giving unexpected results, it is not inventive to discover optimal or workable ranges by routine experimentation. In re Aller, 220 F. 2d454, 105 USQ 233, 235 (CCPA 1995).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kawabata et al. (US 20050218441 A1), and further in view of Iwamoto et al. (US 20070210414 A1), Li (US 20220246625 A1), and Yang et al. (US 20230345786 A1).
Regarding dependent claim 5, Kawabata, further in view of Iwamoto and Li, teach the semiconductor device of claim 4; however, Kawabata remains silent on the semiconductor device further comprising:
a second metal structure, disposed above the second dielectric layer, wherein the second dielectric layer comprises a second recess structure for accommodating the second metal structure.
However, in the same field of endeavor, Yang (US 20230345786 A1) teaches an interconnect structure (Fig. 15) similar to that shown in Fig. 2G of Li. Yang’s conductive contact 550, i.e., a second metal structure, is considered analogous to Li’s conductive layer 132; wherein Yang teaches an analogous second dielectric layer, i.e., dielectric capping layer 570, which comprises a second recess structure (Fig. 15; recess structure of dielectric capping layer 570) for accommodating the second metal structure (Fig. 15). Further, the relationship between Yang’s second metal structure & second recess structure teaches a second metal structure, disposed above the second dielectric layer, wherein the second dielectric layer comprises a second recess structure for accommodating the second metal structure. Thus, modifying the semiconductor device of Kawabata, further in view of Iwamoto and Li, and the second dielectric layer of Kawabata, further in view of Li, as disclosed by Yang would lead to the semiconductor device structure including a second metal structure, disposed above the second dielectric layer, wherein the second dielectric layer comprises a second recess structure for accommodating the second metal structure.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the semiconductor device of Kawabata, further in view of Iwamoto and Li, to include Yang’s second metal structure, because such a modification is the result of combining prior art elements according to known methods to yield predictable results. More specifically, the semiconductor device of Kawabata, further in view of Iwamoto and Li, as modified by Yang’s second metal structure can yield a predictable result of connecting the efuse structure/circuit to upper wiring. Since the claimed invention is merely a combination of old elements, and in the combination each element merely would have performed the same function as it did separately, one of ordinary skill in the art would have recognized that the results of the combination were predictable before the effective filing date of the instant invention.
Further, it would have been obvious to one of ordinary skill in the art before the effective filing date of the instant invention to modify the second insulating layer of Kawabata, further in view of Li, to include Yang’s insulating structure wherein the second dielectric layer comprises a second recess structure for accommodating the second metal structure, because such a modification is based on the use of known techniques to improve similar devices in the same way. More specifically, Yang’s insulating structure is comparable to the second insulating layer of Kawabata, further in view of Li, because of their purpose, position, and function. Therefore, it is within the capabilities of one of ordinary skill in the art to modify the second insulating layer of Kawabata, further in view of Li, to include Yang’s insulating structure wherein the second dielectric layer comprises a second recess structure for accommodating the second metal structure with the predictable result of helping the conducting via structure be aligned to the connect to the efuse circuitry, as well as preventing the diffusion of impurities from the doped layer and doped structure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US 20160359110 A1 – considered for Fig. 5.
US 20030186507 A1 – considered for Fig. 1H.
US 20060050559 A1 – considered for Fig. 3B.
US 20100230780 A1 – considered for Figs. 7 – 13.
US 20120032261 A1 – considered for Fig. 3A.
US 20140015030 A1 – considered for the HVG structure in Fig. 2.
US 20160329282 A1 – considered for Figs. 2A – 2C.
US 20150357491 A1 – considered for Fig. 1.
US 8603918 B2 – considered for Figs. 15 – 16.
US 20240206156 A1 – considered for Figs. 1A – 2.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARIO A AUTORE whose telephone number is (571)270-0059. The examiner can normally be reached Monday - Friday, 8 am - 5 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached on (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
MARIO A. AUTORE JR.
Examiner
Art Unit 2897
/MARIO ANDRES AUTORE JR/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
Prosecution Insights