DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 13 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. [US 2022/0326617 A1].
Regarding claim 13, Park et al. discloses a method of fabricating a semiconductor device (paragraph [0002]), the method comprising:
forming a photoresist layer on an upper surface of a wafer (Fig. 1 item 300, see also paragraph [0027]);
exposing a portion of the photoresist layer to light to form an exposed region of the photoresist layer (LP, see also paragraph [0028]);
producing a first developer having a first temperature (paragraph [0042]) by adjusting a temperature of a developer (paragraph [0055]) by using a temperature adjuster (Figs. 4 and 5 item 456) that is connected to a first nozzle through a pipe, wherein the first nozzle is above the upper surface of the wafer (paragraph [0027]);
providing the first developer to the photoresist layer from the first nozzle; etching a portion of the exposed region by using the first developer (paragraph [0028]);
producing a second developer having a second temperature by adjusting the temperature of the developer (paragraph [0048]) by using the temperature adjuster (455), wherein the second temperature is lower than the first temperature (paragraph [0047] teaches second developer with a second temperature may be lower than the first temperature);
providing the second developer to the photoresist layer from the first nozzle; and etching a remaining portion of the exposed region by using the second developer (as shown in Figs. 9 and 10).
Regarding claim 19, Park et al. discloses wherein the first temperature is from 20° C. to 40° C., and the second temperature is from 5° C. to 25° C (paragraphs [0054] and [0055]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-12, 14-18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. in view of Miura et al. [US 2021/0333707 A1].
Regarding claims 1, 14-18 and 20, Park et al. discloses a method of fabricating a semiconductor device (paragraph [0002]), the method comprising:
forming a photoresist layer on an upper surface of a wafer (Fig. 1 item 300, see also paragraph [0027]);
exposing a portion of the photoresist layer to light to form an exposed region of the photoresist layer and an unexposed region of the photoresist layer (LP, see also paragraph [0028]);
etching a first portion of the exposed region by using a first developer (paragraph [0028]) having a first temperature (paragraph [0042]); and
etching (as shown in Figs. 9 and 10) a second portion of the exposed region by using a second developer having a second temperature (paragraph [0048]) that is lower than the first temperature (paragraph [0047] teaches second developer with a second temperature may be lower than the first temperature).
Park et al. does not teach lowering a temperature of the photoresist layer by using cooling gas.
However, Miura et al. discloses a nozzle unit for use in a liquid treatment apparatus (Fig. 1) that performs a liquid treatment on a substrate wherein a cooling gas in supplied to the surface of the substrate such that it is possible to improve the uniformity of the line width (CD) of the resist film (R) in the processed (developed) workpiece (W) (paragraph [0155], see also Fig. 12).
Therefore, it would have been obvious to one of ordinary skill in the art to provide a cooling gas in supplied to the surface of the substrate, as taught by Miura et al. in the method of Park et al. because such a modification provides improvement of the uniformity of the line width (CD) of the resist film (R) in the processed (developed) workpiece (W) (paragraph [0155] of Miura et al.).
Regarding claim 2, Miura et al. discloses further comprising: drying and removing the first developer by using the cooling gas while the lowering the temperature of the photoresist layer by using the cooling gas (as shown in Fig. 12, see also paragraph [0155]).
Regarding claim 3, Park et al. discloses wherein the first temperature is from 20° C. to 40° C., and the second temperature is from 5° C. to 25° C (paragraphs [0054] and [0055]).
Regarding claim 4, Park et al. in view of Miura et al. discloses further comprising: providing the first developer (paragraph [0042] of Park et al.) to the photoresist layer from a first nozzle that is above the upper surface of the wafer (paragraph [0027] of Park et al.), before the etching the first portion of the exposed region; and providing the cooling gas to the photoresist layer from a second nozzle that is above the upper surface of the wafer, before the lowering the temperature of the photoresist layer (as shown in Fig. 12, see also paragraph [0155] of Miura et al.).
Regarding claim 5, Park et al. discloses further comprising: providing the second developer (paragraph [0048]) to the photoresist layer from the first nozzle, before the etching the second portion of the exposed region (as shown in Figs. 9 and 10).
Regarding claim 6, Park et al. discloses further comprising: producing the first developer having the first temperature by adjusting a temperature of a developer by using a first temperature adjuster that is connected to the first nozzle through a first pipe, before the providing the first developer to the photoresist layer from the first nozzle; and producing the second developer having the second temperature by adjusting the temperature of the developer by using the first temperature adjuster, before the providing the second developer to the photoresist layer from the first nozzle (as shown in Figs. 4 and 5, see also paragraphs [0047]-[0048]).
Regarding claim 7, Park et al. in view of Miura et al. discloses further comprising: providing the second developer to the photoresist layer from a third nozzle that is above the upper surface of the wafer, before the etching the second portion of the exposed region (as shown in Figs. 4 and 5, see also paragraphs [0047]-[0048] of Park et al. and Fig. 1 of Miura et al.).
Regarding claim 8, Park et al. discloses further comprising: producing the first developer having the first temperature by adjusting a temperature of a developer by using a first temperature adjuster that is connected to the first nozzle through a first pipe, before the providing the first developer to the photoresist layer from the first nozzle; and producing the second developer having the second temperature by adjusting the temperature of the developer by using a second temperature adjuster connected to the third nozzle through a second pipe, before the providing the second developer to the photoresist layer from the third nozzle (as shown in Figs. 4 and 5, see also paragraphs [0047]-[0048] of Park et al. and Fig. 1 of Miura et al.).
Regarding claim 9 and 10, Park et al. discloses further comprising: heating the wafer to increase the temperature of the photoresist layer while the etching the first portion of the exposed region by using the first developer, wherein the heating the wafer includes heating an edge region of the wafer to increase a temperature of an edge region of the photoresist layer. (paragraph [0042]).
Regarding claim 11, Miura et al. discloses wherein the cooling gas includes nitrogen (paragraph [007]).
Regarding claim 12, Park et al. discloses wherein the etching of the second portion of the exposed region by using the second developer having the second temperature includes maintaining the unexposed region of the photoresist layer without etching (paragraph [0028] and [0047]-[0048]).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEORAM PERSAUD whose telephone number is (571)270-5476. The examiner can normally be reached M-F 8AM-5PM.
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/DEORAM PERSAUD/Primary Examiner, Art Unit 2882
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