DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of species VIII in the reply filed on 04/27/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 05/08/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Objections
Claims 2 and 3 are objected to because of the following informalities:
Claims 2 and 3 recite in line 2 “grearter.” It should be -- greater--.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, 4, 6, 7, 9-10, 12-13, 15-16 and 18-19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 2014/0169068 A1).
Regarding claim 1, Lee further teaches the memory operation method, comprising:
applying a first programming signal to at least one memory cell, wherein a first pulse voltage of the first programming signal is less than a target voltage (Fig. 8, the memory device applies a plurality of program signals until the target threshold voltage is reached);
applying a second programming signal to the at least one memory cell, wherein a magnitude of the second programming signal is less than a magnitude of the first programming signal (Fig. 8, Lee teaches decrement step pulse program (DSPP) where the second programming loop uses a program signal less than the first programming loop); and
reading a programming state of the at least one memory cell to determine whether the programming state matches a target state corresponding to the target voltage (Fig. 8, verify operation VF is performed after each programming loop to determine if the target voltage is reached).
Regarding claim 2, Lee further teaches the memory operation method of claim 1, wherein the first pulse voltage of the first programming signal is greater than a second pulse voltage of the second programming signal (Fig. 8, 1st PGM is greater than 2nd PGM).
Regarding claim 4, Lee further teaches the memory operation method of claim 1, wherein the first programming signal is applied to the at least one memory cell in a first run, the second programming signal is applied to the at least one memory cell in a second run, and the second run is executed after the first run (Fig. 8, programming loops are applied to a plurality of memory cells).
Regarding claim 6, Lee further teaches the memory operation method of claim 1, further comprising: applying a third programming signal to the at least one memory cell, wherein a magnitude of the third programming signal is less than the magnitude of the second programming signal, and a magnitude difference between the first programming signal and the second programming signal is equal to a magnitude difference between the second programming signal and the third programming signal (Fig. 8, third programming signal 3rd PGM. The difference between the program signal is the same).
Regarding claim 7, Lee further teaches the memory operation method of claim 1, wherein the at least one memory cell comprises a plurality of memory cells, and applying the second programming signal to the at least one memory cell comprises: applying the second programming signal to the plurality of memory cells after applying the first programming signal to the plurality of memory cells in sequence (Fig. 8 second programming signal is applied after the first programming loop. See Fig. 9A and 9B, the programming loop is applied to multiple memory cells).
Regarding claims 9-10, 12-13, 15-16 and 18-19, the claims have similar limitations as claim above. Therefore, the claims are rejected under the same grounds of rejection.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 3, 11 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Huang (US 2021/0350853 A1).
Regarding claim 3, Lee is silent in teaching wherein a first pulse time of the first programming signal is greater than a second pulse time of the second programming signal.
Huang teaches a first pulse time of the first programming signal is greater than a second pulse time of the second programming signal (Fig. 6, the pulse time is decremented in sequence programming operation. Huang teaches fixed, incremented and decremented pulse width during the program operation which is within knowledge of a skilled person in the art, see Fig. 3A and Fig. 3B).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to adjust the width of the programming signal in order to enhance programming performance, see ¶0044.
Regarding claims 11 and 17, the claims have similar limitations as claim 3. Therefore, the claims are rejected under the same grounds of rejection.
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 1 above, and further in view of Lin et al. (US 2014/0047160 A1).
Regarding claim 5, Lee teaches applying a step program voltages instead of applying a single program voltage (Fig. 8), applying a single program voltage can result in over programming. The initial step up or step down voltages are usually lower than the single pulse applied to a memory cell to bring it to a target voltage, to prevent over programming. Lee did not explicitly teach wherein the first pulse voltage is between 70% and 80% of the target voltage.
Lin teaches the first pulse voltage is between 70% and 80% of the target voltage ¶0115).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to use a lower programming voltages than the initial programming voltage which would take the memory cell to the target level in order to manage the wear degree of the memory cell.
Claim(s) 8, 14, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claim 7 above, and further in view of Neale et al. (US 4,228,524).
Regarding claim 8, Lee did not explicitly teach wherein a time length that the first programming signal is applied to the plurality of memory cells is between 1 and 100 milliseconds. However, the exact duration for the program pulse can be changed by any person with the ordinary skills in the art based on the design requirements. To expedite the prosecution of the case Neale et al. is used to teach the first programming signal is applied to the plurality of memory cells is between 1 and 100 milliseconds (Col. 1, lines 10-35).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to have a pram signal between 1 and 100 milliseconds based on the design requirements.
Regarding claims 14 and 20, the claims have similar limitations as claim 8. Therefore, the claims are rejected under the same grounds of rejection.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
Prosecution Insights