DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Chowdhury et al. (US 2020/0235090).
Regarding claim 1, Chowdhury discloses a semiconductor memory device, comprising:
a lower structure (900, fig. 15A and paragraph 0128); and
an upper structure on the lower structure (700, fig. 15A and paragraph 0128),
wherein the upper structure includes:
a first substrate (708, fig. 15A);
an upper wiring line on the first substrate (716, fig. 15A);
a lower power line in a lower portion of the first substrate (784, fig. 15A and paragraph 0132); and
a first bonding pad between the lower power line and the lower structure (788, fig. 15A and paragraph 0132),
wherein the lower power line and the first bonding pad are electrically connected to
each other (fig. 15A and paragraph 0132), and
wherein the upper structure is electrically connected through the first bonding pad to the
lower structure (fig. 15A and paragraph 0132).
Regarding claim 2, Chowdhury futher discloses wherein the lower structure includes a second bonding pad (144, fig. 15A and paragraph 0132),
wherein the first bonding pad and the second bonding pad directly contact each other (788, 144, fig. 15A and paragraph 0132).
Regarding claim 3, Chowdhury further discloses wherein the lower structure (900, fig. 15A) further includes:
a second substrate (9, fig. 15A);
a data storage pattern on the second substrate (55, fig. 15A and paragraph 0081);
a landing pad on the data storage pattern;
a channel pattern (60, fig. 15A and paragraph 0083) on the landing pad, wherein the landing pad electrically connects the
channel pattern and the data storage pattern to each other;
a word line (46, fig. 15A and paragraph 0100) adjacent to the channel pattern; and
a bit line (fig. 15A and paragraph 0117) on the channel pattern,
wherein the bit line extends in a first direction (fig. 15A), and
wherein the word line extends in a second direction (fig. 15A) that intersects the first direction.
Regarding claim 4, Chowdhury further discloses a lower wiring line between the bit line and the second bonding pad (124, fig. 15A and paragraph 0119),
wherein the lower wiring line is electrically connected to the second bonding pad (144, fig. 15A).
Regarding claim 5, Chowdhury further discloses a deep device isolation pattern that extends through the first substrate (711, fig. 15A and paragraph 0133).
Regarding claim 6, Chowdhury further discloses a backside through via (712, fig. 15A and paragraph 0133) that extends through the deep device isolation pattern (711, fig. 15A and paragraph 0133),
wherein the backside through via electrically connects the upper wiring line and the
lower power line to each other (fig. 15A).
Regarding claim 7, Chowdhury further discloses wherein a width of the backside through via decreases with distance in a direction perpendicular to a top surface of the lower power line extending away from the lower structure (fig. 15A).
Regarding claim 8, Chowdhury further discloses a transistor on the first substrate (710, fig. 15A and paragraph 0131);
a plurality of source/drain patterns on opposite sides of the transistor (742, fig. 15A and paragraph 0131); and
an active contact electrically connected to each of the source/drain patterns (fig. 15A),
wherein the active contact is electrically connected to the backside through via (fig. 15A and paragraph 0131).
Regarding claim 9, Chowdhury further discloses a power delivery network layer between the lower power line and the lower structure, wherein the power delivery network layer is configured to apply a voltage to the lower power line (784, fig. 15A).
Regarding claim 10, Chowdhury further discloses a nitride pattern between the upper structure and the lower structure (760, fig. 15A and paragraph 0132).
Regarding claim 11, Chowdhury discloses a semiconductor memory device, comprising:
a lower structure (900, fig. 15A and paragraph 0128); and
an upper structure on the lower structure (700, fig. 15A and paragraph 0128),
wherein the upper structure includes:
a first substrate (708, fig. 15A);
an upper wiring line on the first substrate (716, fig. 15A);
a lower power line in a lower portion of the first substrate (784, fig. 15A and paragraph 0132); and
a first bonding pad between the lower power line and the lower structure (788, fig. 15A and paragraph 0132),
wherein the lower structure includes:
a second substrate (9,fig. 15A) that includes a cell region (above 9, fig. 15A); and
a second bonding pad on the cell region (144, fig. 15A and paragraph 0126),
wherein the first bonding pad is exposed through a rear surface of the upper structure (788, fig. 15A),
wherein the second bonding pad is exposed through a front surface of the lower
structure (144, fig. 15A),
wherein the front surface of the lower structure is in contact with the rear surface of the
upper structure (fig. 15A), and
wherein the first bonding pad and the second bonding pad directly contact each other (fig. 15A and paragraph 0132).
Regarding claim 12, Chowdhury further discloses a backside through via that extends through the first substrate and electrically connects the upper wiring line to the lower power line (712, fig. 15A).
Regarding claim 13, Chowdhury further discloses wherein the first bonding pad (788, fig. 15A) is electrically connected to the lower power line (fig. 15A), and
the second bonding pad is electrically connected to a lower wiring line on the cell
region (144, fig. 15A).
Regarding claim 14, Chowdhury further discloses wherein the lower structure (900, fig. 15A) further includes:
a data storage pattern on the second substrate (55, fig. 15A and paragraph 0081);
a landing pad on the data storage pattern;
a channel pattern (60, fig. 15A and paragraph 0083) on the landing pad, wherein the landing pad electrically connects the
channel pattern and the data storage pattern to each other;
a word line (46, fig. 15A and paragraph 0100) adjacent to the channel pattern; and
a bit line (fig. 15A and paragraph 0117) on the channel pattern,
wherein the bit line extends in a first direction (fig. 15A), and
wherein the word line extends in a second direction (fig. 15A) that intersects the first direction.
Regarding claim 15, Chowdhury further discloses a power delivery network layer between the lower power line and the lower structure, wherein the power delivery network layer is configured to apply a voltage to the lower power line (784, fig. 15A).
Regarding claim 16, Chowdhury discloses a semiconductor memory device, comprising:
a lower structure (900, fig. 15A);
an upper structure on the lower structure (700, fig. 15A); and
a bonding structure between the lower structure and the upper structure (788, 144, fig. 15A and paragraph 0132),
wherein the upper structure includes:
a first substrate (708, fig. 15A);
an upper wiring line on the first substrate (716, fig. 15A);
a lower power line in a lower portion of the first substrate (784, fig. 15A and paragraph 0132); and
a backside through via that extends through the first substrate and connects the
upper wiring line to the lower power line (712, fig. 15A),
wherein the lower structure includes:
a second substrate that includes a cell region (9, fig. 15A); and
a lower wiring layer on the cell region (128, 124, 126, fig. 15A and paragraph 0119),
wherein the bonding structure includes:
a first part in a lower portion of the upper structure (788, fig. 15A and paragraph 0132); and
a second part in an upper portion of the lower structure (144, fig. 15A and paragraph 0132),
wherein the bonding structure electrically connects the lower power line and the lower
wiring layer to each other (fig. 15A).
Regarding claim 17, Chowdhury further discloses a transistor on the first substrate (710, fig. 15A and paragraph 0131);
a plurality of source/drain patterns on opposite sides of the transistor (742, fig. 15A and paragraph 0131); and
an active contact electrically connected to each of the source/drain patterns (fig. 15A),
wherein the active contact is electrically connected to the backside through via (fig. 15A and paragraph 0131).
Regarding claim 18, Chowdhury further discloses wherein the lower structure (900, fig. 15A) further includes:
a second substrate (9, fig. 15A);
a data storage pattern on the second substrate (55, fig. 15A and paragraph 0081);
a landing pad on the data storage pattern;
a channel pattern (60, fig. 15A and paragraph 0083) on the landing pad, wherein the landing pad electrically connects the
channel pattern and the data storage pattern to each other;
a word line (46, fig. 15A and paragraph 0100) adjacent to the channel pattern; and
a bit line (fig. 15A and paragraph 0117) on the channel pattern,
wherein the bit line extends in a first direction (fig. 15A), and
wherein the word line extends in a second direction (fig. 15A) that intersects the first direction.
Regarding claim 19, Chowdhury further discloses a power delivery network layer between the lower power line and the lower structure, wherein the power delivery network layer is configured to apply a voltage to the lower power line (784, fig. 15A).
Regarding claim 20, Chowdhury further discloses a deep device isolation pattern that extends through the first substrate (711, fig. 15A and paragraph 0133).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent Application Publication 2024/0063160 discloses a semiconductor memory device with a lower structure and an upper structure bonded together by a bonding pad on the bottom of the upper structure to a bonding pad on the top of the lower structure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DOUGLAS M MENZ whose telephone number is (571)272-1877. The examiner can normally be reached Monday-Friday 8:00am-5:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DOUGLAS M MENZ/Primary Examiner, Art Unit 2897 9/13/26
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