DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 2-15 are objected to because of the following informalities:
Claim 2 (claim 7) recites “the first and second elements” which should be replaced with “the first element and the second element” to avoid antecedent basis issue.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2-6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 2 recites “the metal structure is electrically isolated from the first and second elements”. However, claim 2 recites “the first element further comprising a metal structure connected to a first conductive interface feature of the first plurality of conductive interface features”. Thus, “the metal structure” is electrically connected to a first conductive interface feature of the first element. Thus, it is unclear which particular embodiment applicant is referring to that comprises “the metal structure” electrically connected to a first conductive interface feature of the first element, and “the metal structure is electrically isolated from the first and second elements”. The specification does not resolve ambiguity of the claim and that renders the claim indefinite.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 2-3 and 5-15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2015/0194455 to Ho et al. (hereinafter Ho).
With respect to claim 2, Ho discloses a bonded structure (e.g., a first wafer bonded to a second wafer, see the annotated Fig. 6 below) (Ho, Figs. 1A, 2, 6, ¶0015-¶0027, ¶0038-¶0039, ¶0047-¶0050, ¶0053-¶0055) comprising:
a first element (e.g., a first wafer 200 including a first electrical circuitry 203) (Ho, Fig. 6, ¶0047-¶0048, ¶0023-¶0026) comprising a first plurality of conductive interface features (614A2/614B2) at least partially embedded in a first nonconductive interface feature (210), wherein at least one of the first plurality of conductive interface features (614A2/614B2 and 612B) comprises a first plurality of discrete shapes (e.g., a plurality of conductive rings 614A2/614B2) spaced apart from one another by the first nonconductive interface feature (210), the first element (200) further comprising a metal structure (e.g., seal ring structure 208A/208B formed by a same material as interconnects 206/110 including metals, such as, copper, tungsten, or aluminum) (Ho, Fig. 6, ¶0050, ¶0023-¶0025) connected to a first conductive interface feature (e.g., 614A2) of the first plurality of conductive interface features (614A2/614B2), wherein the metal structure (208A/208B) comprises wide and narrow segments extending vertically
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through at least a portion of the first element (200);
a second element (e.g., a second wafer 100 including a first electrical circuitry 104) (Ho, Fig. 6, ¶0048-¶0049, ¶0016-¶0022) comprising a second plurality of conductive interface features (614A1/614B1) at least partially embedded in a second nonconductive interface feature (112), the second plurality of conductive interface features (614A1/614B1) directly bonded (e.g., metal-to-metal bonding) (Ho, Fig. 6, ¶0048) to the first plurality of conductive interface features (614A2/614B2) and the second nonconductive interface feature (112) directly bonded (e.g., dielectric-to-dielectric bonding) to the first nonconductive interface feature (210); and
a first electronic component (e.g., BSI sensor of the second wafer 100 of the stacked/bonded structure10 surrounded by the seal ring in Fig. 2) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038), wherein the first plurality of discrete shapes (e.g., seal ring structure 614A2/614B2) is disposed in a ring about the first electronic component (e.g., BSI sensor of the second wafer 100), and wherein the metal structure (e.g., seal ring structure 208A/208B formed by a same material as interconnects 206/110 including metals, such as, copper, tungsten, or aluminum ) (Ho, Fig. 6, ¶0050, ¶0023-¶0025) is electrically isolated (e.g., by the dielectric layer 204 and the dielectric layers 108 and 106) from the first and second elements (e.g., electrical circuitry 203 of the first wafer 200 and electrical circuitry 104 of the second wafer 100).
Regarding claim 3, Ho discloses the bonded structure of Claim 2. Further, Ho discloses the bonded structure, wherein the metal structure (e.g., seal ring structure 208A/208B formed by metals to prevent peeling and chipping of the wafer during singulating process that is interpreted as a crack stopper) (Ho, Fig. 6, ¶0038) is a crack stopper.
Regarding claim 5, Ho discloses the bonded structure of Claim 2. Further, Ho discloses the bonded structure, wherein the metal structure (e.g., seal ring structure 208A/208B formed by metals to prevent peeling and chipping of the wafer during singulating process) (Ho, Fig. 6, ¶0024) extends continuously about a periphery of the first electronic component.
Regarding claim 6, Ho discloses the bonded structure of Claim 2. Further, Ho discloses the bonded structure, wherein the first electronic component (e.g., BSI sensor of the integrated circuit 104 of the second wafer 100 and capable to sense light is interpreted as an optical component) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038) comprises an optical component.
With respect to claim 7, Ho discloses a bonded structure (e.g., a first wafer bonded to a second wafer) (Ho, Figs. 1A, 2, 6, ¶0015-¶0027, ¶0038-¶0039, ¶0047-¶0050, ¶0053-¶0055) comprising:
a first element (e.g., a first wafer 100 including an electrical circuitry 104 or a second wafer 200 an electrical circuitry 203) (Ho, Fig. 6, ¶0047-¶0049, ¶0016-¶0026) comprising a first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) at least partially embedded in a first nonconductive interface feature (e.g., 112 or 210), wherein at least one of the first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) comprises a first plurality of discrete shapes (e.g., a plurality of conductive rings 614A1/614B1 or 614A2/614B2) spaced apart from one another by the first nonconductive interface feature (112/ or 210), the first element (100 or 200) further comprising a first connecting element (e.g., seal ring structure 616A/616B or 208A/208B formed by a same material as interconnects 206/110 including metals, such as, copper, tungsten, or aluminum) (Ho, Fig. 6, ¶0048, ¶0023-¶0025) to provide a first mechanical connection to a first conductive interface feature (e.g., 614A1/614A2) of the first plurality of conductive interface features (614A1/614B1 or 614A2/614B2), wherein the first connecting element (616A/616B or 208A/208B) extends vertically through at least a portion of the first element (100 or 200), and wherein the first connecting element (616A/616B or 208A/208B) comprise a metal structure (e.g., seal ring structure 616A/616B or 208A/208B formed by a same material as interconnects 206/110 including metals, such as, copper, tungsten, or aluminum) (Ho, Fig. 6, ¶0048, ¶0023-¶0025), the metal structure (616A/616B or 208A/208B) comprising alternating wide and narrow segments;
a second element (e.g., a second wafer 200 or 100 including an electrical circuitry 203 or 104) (Ho, Fig. 6, ¶0047-¶0049, ¶0016-¶0026) comprising a second plurality of conductive interface features (614A2/614B2 or 614A1/614B1) at least partially embedded in a second nonconductive interface feature (210/112), the second plurality of conductive interface features (614A2/614B2 or 614A1/614B1) directly bonded (e.g., metal-to-metal bonding) (Ho, Fig. 6, ¶0048) to the first plurality of conductive interface features (614A1/614B1 or 614A2/614B2) and the second nonconductive interface feature (210/112) directly bonded (e.g., dielectric-to-dielectric bonding) to the first nonconductive interface feature (112/210), wherein the metal structure (616A/616B or 208A/208B) provides the first mechanical connection between the first element (100/200) and the second element (200/100); and
an integrated device (e.g., BSI sensor or the integrated circuit 203 of the integrated circuit 104/203 of the first/second wafer 100/200 of the stacked/bonded structure 10 surrounded by the seal rings, as in Fig. 2) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038), wherein the first plurality of discrete shapes (e.g., seal ring structure 614A1/614B1 or 614A2/614B2) is disposed in a ring about the integrated device, and wherein the metal structure (616A/616B or 208A/208B) (Ho, Figs. 2, 6, ¶0024, ¶0038) extends continuously about a periphery of the integrated device.
Regarding claim 8, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein the integrated device (e.g., BSI sensor of the integrated circuit 104 of the first wafer 100 and capable to sense light is interpreted as an optical component) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038) comprises an optical component.
Regarding claim 9, Ho discloses the bonded structure of Claim 8. Further, Ho discloses the bonded structure, wherein the first element (100) comprises the first optical device (e.g., BSI sensor of the integrated circuit 104 of the first wafer 100) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038).
Regarding claim 10, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein the first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) (Ho, Figs. 2, 6, ¶0047-¶0048, ¶0030, ¶0039) comprises an array of multiple rings of discrete shapes disposed about the integrated device (104).
Regarding claim 11, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein one or more of the second plurality of conductive interface (614A2/614B2 and 612B or 614A1/614B1 and 612A) (Ho, Figs. 2, 6, ¶0047-¶0049, ¶0039) features comprises a second plurality of discrete shapes spaced apart by the second nonconductive interface feature (210/112).
Regarding claim 12, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein the metal structure (208A/208B) (Ho, Fig. 6, ¶0048, ¶0023-¶0025) comprises a first segment (e.g., an upper metal line of the interconnect) at a first vertical location below a bonding surface of the bonded structure (100/200) and a second segment (e.g., an upper via of the interconnect) at a second vertical location below the bonding surface, the first segment wider than the second segment.
Regarding claim 13, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein no cavity is provided between the first and second elements (100 and 200) (Ho, Fig. 6, ¶0047-¶0049).
Regarding claim 14, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein at least one of the first and second elements (100/200) comprises a processor die (e.g., the wafer 200 includes logic circuit, such as data processing circuit) (Ho, Fig. 6, ¶0026-¶0027).
Regarding claim 15, Ho discloses the bonded structure of Claim 7. Further, Ho discloses the bonded structure, wherein at least one of the first and second elements (100/200) comprises a sensor die (e.g., the wafer 100 includes a backside illuminated sensor) (Ho, Fig. 6, ¶0026, ¶0030).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Regarding claim 4, Ho discloses the bonded structure of Claim 2. Further, Ho does not specifically disclose that the first electronic component is electrically connected to ground.
However, Wahl teaches forming an integrated chip (Wahl, Fig. 4, ¶0033-¶0034) comprising an active circuitry and a chip guard ring structure including a dense configuration of vias (404,408) and metal lines (406, 410) as a protective metal structure around the active circuitry and connected to a ground potential, to protect the chip circuitry against physical damage including cracks propagating into the chip region and electrical damage (e.g., ESD).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the bonding structure of Ho by forming the first electronic component including the chip guard ring structure held at a grounding potential as taught by Wahl to have the bonding structure, wherein the first electronic component is electrically connected to ground, in order to protect the chip circuitry against physical damage including cracks propagating into the chip region and electrical damage (e.g., ESD) (Wahl, ¶0033-¶0034).
Claims 16-21 are rejected under 35 U.S.C. 103 as being unpatentable over US 2015/0194455 to Ho in view of Wahl et al. (US 2011/0095392, hereinafter Wahl).
With respect to claim 16, Ho discloses a bonded structure (e.g., a first wafer bonded to a second wafer) (Ho, Figs. 1A, 2, 6, ¶0015-¶0027, ¶0038-¶0039, ¶0047-¶0050, ¶0053-¶0055) comprising:
a first element (e.g., a first wafer 100 including an electrical circuitry 104 or a second wafer 200 an electrical circuitry 203) (Ho, Fig. 6, ¶0047-¶0049, ¶0016-¶0026) comprising a first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) at least partially embedded in a first nonconductive interface feature (e.g., 112 or 210), wherein at least one of the first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) comprises a first plurality of discrete shapes (e.g., a plurality of conductive rings 614A1/614B1 or 614A2/614B2) spaced apart from one another by the first nonconductive interface feature (112/ or 210), the first element (100 or 200) further comprising a metal structure (e.g., seal ring structure 616A/616B or 208A/208B formed by a same material as interconnects 206/110 including metals, such as, copper, tungsten, or aluminum) (Ho, Fig. 6, ¶0048, ¶0023-¶0025) connected to a first conductive interface feature (e.g., 614A1 or 614A2) of the first plurality of conductive interface features (614A1/614B1 or 614A2/614B2), wherein the metal structure (616A/616B or 208A/208B) comprises wide and narrow segments extending vertically through at least a portion of the first element (100 or 200);
a second element (e.g., a second wafer 200 or 100 including an electrical circuitry 203 or 104) (Ho, Fig. 6, ¶0047-¶0049, ¶0016-¶0026) comprising a second plurality of conductive interface features (614A2/614B2 or 614A1/614B1) at least partially embedded in a second nonconductive interface feature (210/112), the second plurality of conductive interface features (614A2/614B2 or 614A1/614B1) directly bonded (e.g., metal-to-metal bonding) (Ho, Fig. 6, ¶0048) to the first plurality of conductive interface features (614A1/614B1 or 614A2/614B2) and the second nonconductive interface feature (210/112) directly bonded (e.g., dielectric-to-dielectric bonding) to the first nonconductive interface feature (112/210); and
a first electronic component (e.g., BSI sensor or the integrated circuit 203 of the integrated circuit 104/203 of the first/second wafer 100/200 of the stacked/bonded structure 10 surrounded by the seal rings, as in Fig. 2) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038) coupled to or formed with the first element (100/200) or the second element (200/100), wherein the first plurality of discrete shapes (614A1/614B1 or 614A2/614B2) is disposed in a ring about the first electronic component.
Further, Ho does not specifically disclose that the metal structure electrically connects to ground.
However, Wahl teaches forming an integrated chip (Wahl, Fig. 4, ¶0033-¶0034) comprising an active circuitry and a chip guard ring structure including a dense configuration of vias (404,408) and metal lines (406, 410) as a protective metal structure around the active circuitry and connected to a ground potential, to protect the chip circuitry against physical damage including cracks propagating into the chip region and electrical damage (e.g., ESD).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the bonding structure of Ho by forming the chip guard ring structure held at a grounding potential as taught by Wahl to have the bonding structure, wherein the metal structure electrically connects to ground, in order to protect the chip circuitry against physical damage including cracks propagating into the chip region and electrical damage (e.g., ESD) (Wahl, ¶0033-¶0034).
Regarding claim 17, Ho in view of Wahl discloses the bonded structure of Claim 16. Further, Ho discloses the bonded structure, wherein the metal structure (e.g., seal ring structure 208A/208B) (Ho, Fig. 6, ¶0024) extends continuously about the first electronic component.
Regarding claim 18, Ho in view of Wahl discloses the bonded structure of Claim 16. Further, Ho discloses the bonded structure, wherein the metal structure (e.g., seal ring structure 208A/208B formed to prevent peeling and chipping of the wafer during singulating process) (Ho, Fig. 6, ¶0038) is a crack stopper.
Regarding claim 19, Ho in view of Wahl discloses the bonded structure of Claim 16. Further, Ho discloses the bonded structure, wherein the first plurality of conductive interface features (614A1/614B1 and 612A or 614A2/614B2 and 612B) (Ho, Figs. 2, 6, ¶0047-¶0048, ¶0030, ¶0039) comprises an array of multiple rings of discrete shapes disposed about a periphery of the first electronic component (e.g., 104, BSI sensor of the integrated circuit 104 of the first wafer 100 of the stacked/bonded structure 10 surrounded by the seal rings, as in Fig. 2) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038).
Regarding claim 20, Ho n view of Wahl discloses the bonded structure of Claim 16. Further, Ho discloses the bonded structure, wherein the ring (e.g., a plurality of conductive rings 614A1/614B1 or 614A2/614B2) is disposed around the first electronic component (e.g., 104, BSI sensor of the integrated circuit 104 of the first wafer 100 of the stacked/bonded structure 10 surrounded by the seal rings, as in Fig. 2) (Ho, Figs. 2, 6, ¶0048-¶0049, ¶0030, ¶0038) to define an effectively closed profile (e.g., a ring profile) to connect the first and second elements (100/ and 200).
Regarding claim 21, Ho n view of Wahl discloses the bonded structure of Claim 20. Further, Ho discloses the bonded structure, wherein the effectively closed profile (e.g., a ring profile as in Fig. 2) substantially seals an interior region of the bonded structure from water and chemicals diffusing into the interior region (Ho, Figs. 2, 6, ¶0024-¶0049, ¶0030, ¶0038), but does not specifically disclose that the effectively closed profile substantially seals an interior region of the bonded structure from gases diffusing into the interior region.
However, Ho teaches that the seal ring structure (Ho, Figs. 2, 6, ¶0053) formed at the bonding interface is not porous and thus prevents the penetration of various contaminants from entering the bonding interface to increase the yield of the stacked structure.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to modify the bonding structure of Ho/Wahl by forming the seal ring structure at the bonding interface as taught by Ho to have the bonding structure, wherein the metal structure electrically connects to ground, in order to protect the chip circuitry against physical damage including cracks propagating into the chip region and electrical damage (e.g., ESD) (Wahl, ¶0033-¶0034).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NATALIA GONDARENKO whose telephone number is (571)272-2284. The examiner can normally be reached 9:30 AM-7:30 PM.
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/NATALIA A GONDARENKO/Primary Examiner, Art Unit 2891
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