DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/13/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
“a recording unit that generates control data” in claims 3 and 16, with the corresponding structure as specified in Paragraphs [106]-[108] and Paragraphs [0115]-[0118] of Applicant’s Specification filed 09/13/2024.
“a control unit that: directs the second operation” in claims 1, 15, and 20, with the corresponding structure as specified in Paragraphs [0106]-[0108] and Paragraphs [0118]-[0119] of Applicant’s Specification filed 09/13/2024.
“a synchronization unit that sends a signal” in claims 10 and 16, with the corresponding structure as specified in Paragraphs [0120] and [0160] of Applicant’s Specification filed 09/13/2024.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-18 of U.S. Patent No. 12,189,564. Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-18 of US Patent No. 12,189,564 disclose all of the features of claims 1-20 of the Instant Application.
As per claims 1-20,
Instant Application
US Patent 12,189,564 (US Application 18/109,590)
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to: implement a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; implement a second operation that receives the output of the first operation as an input; and wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuity, comprising: a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to implement: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; a second operation that receives the output of the first operation as an input; and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output; and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 7: The data processing system of claim 1, wherein the reconfigurable processor is further configured to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 8: The data processing system of claim 7, wherein the reconfigurable processor is configured to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 1 of US Patent 12,189,564 teaches the bolded, underlined, and italicized limitations of Instant Claim 1.
Claim 7 of US Patent 12,189,564 teaches the bolded limitations of Instant Claim 1.
Claim 8 of US Patent 12,189,564 teaches the underlined limitations of Instant Claim 1.
Claim 2: The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units that implement the first and second operations.
Claim 2: The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units that implement the first and second operations.
Claim 3: The data processing system of claim 1, wherein the control circuitry further comprises: a recording unit that generates control data that is indicative of the size of the output.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to implement: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; a second operation that receives the output of the first operation as an input; and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output; and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 4: The data processing system of claim 3, wherein the recording unit generates the control data while the first operation generates the output.
Claim 3: The data processing system of claim 1, wherein the recording unit generates the control data while the first operation generates the output.
Claim 5: The data processing system of claim 4, wherein the recording unit comprises: a counter that counts a number of elements in the output to generate the control data.
Claim 4: The data processing system of claim 3, wherein the recording unit comprises: a counter that counts a number of elements in the output to generate the control data.
Claim 6: The data processing system of claim 5, wherein the counter increments conditionally based on a predicate of the first operation.
Claim 5: The data processing system of claim 4, wherein the counter increments conditionally based on a predicate of the first operation.
Claim 7: The data processing system of claim 3, wherein the control unit fetches the control data from the recording unit.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to implement: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; a second operation that receives the output of the first operation as an input; and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output; and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 8: The data processing system of claim 7, wherein the control unit provides the control data to the second operation, wherein the second operation processes the input based on the control data.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to implement: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; a second operation that receives the output of the first operation as an input; and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output; and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 9: The data processing system of claim 7, further comprising: external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to implement: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; a second operation that receives the output of the first operation as an input; and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output; and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the second operation processes the input based on the control data; and external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 10: The data processing system of claim 1, wherein the control circuitry further comprises: a synchronization unit that sends a signal to the second operation when the first operation has generated the output.
Claim 6: The data processing system of claim 1, wherein the reconfigurable processor is further configured to implement a synchronization unit that informs the second operation when the first operation has generated the output.
Claim 11: The data processing system of claim 10, wherein the reconfigurable processor is configured to enable the first operation to write, when the first operation has finished writing the first portion of the output and the second operation has finished reading the first portion of the input, a second portion of the output to the second portion of the buffer, while the second operation reads the first portion of the output from the first portion of the buffer as a second portion of the input.
Claim 9: The data processing system of claim 8, wherein the reconfigurable processor is configured to enable the first operation to write, when the first operation has finished writing the first portion of the output and the second operation has finished reading the first portion of the input, a second portion of the output to the second portion of the buffer, while the second operation reads the first portion of the output from the first portion of the buffer as a second portion of the input.
Claim 12: The data processing system of claim 1, further comprising: a compiler that generates configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry.
Claim 10: The data processing system of claim 1, further comprising: a compiler that generates configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, the recording unit, and the control unit.
Claim 13: The data processing system of claim 12, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, and wherein the compiler generates in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements.
Claim 11: The data processing system of claim 10, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, and wherein the compiler generates in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements.
Claim 14: The data processing system of claim 1, further comprising: runtime logic that is configured to program the reconfigurable processor with configuration data such that the reconfigurable processor implements the first operation, the second operation, and the control circuitry.
Claim 12: The data processing system of claim 1, further comprising: runtime logic that is configured to program the reconfigurable processor with configuration data such that the reconfigurable processor implements the first operation, the second operation, the recording unit, and the control unit.
Claim 15: A method of operating a data processing system that comprises a reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises: a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 13: A method of operating a data processing system that comprises a reconfigurable processor and external memory coupled to the reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, and control circuitry that comprises: a recording unit that generates control data that is indicative of the size of the output, and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the control unit stores the control data in the external memory, wherein the second operation retrieves the control data from the external memory, and wherein the second operation processes the input based on the control data.
Claim 7: The data processing system of claim 1, wherein the reconfigurable processor is further configured to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 8: The data processing system of claim 7, wherein the reconfigurable processor is configured to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 13 of US Patent 12,189,564 teaches the bolded, underlined, and italicized limitations of Instant Claim 15.
Claim 7 of US Patent 12,189,564 teaches the bolded limitations of Instant Claim 15.
Claim 8 of US Patent 12,189,564 teaches the underlined limitations of Instant Claim 15.
Claim 16: The method of claim 15, further comprising: configuring the reconfigurable processor such that the control circuitry further comprises: a recording unit that generates control data that is indicative of the size of the output, wherein the control unit provides the control data to the second operation, and wherein the second operation processes the input based on the control data; and a synchronization unit that sends a signal to the second operation when the first operation has generated the output.
Claim 13: A method of operating a data processing system that comprises a reconfigurable processor and external memory coupled to the reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, and control circuitry that comprises: a recording unit that generates control data that is indicative of the size of the output, and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the control unit stores the control data in the external memory, wherein the second operation retrieves the control data from the external memory, and wherein the second operation processes the input based on the control data.
Claim 14: The method of claim 13, further comprising: configuring the reconfigurable processor such that the reconfigurable processor implements a synchronization unit that informs the second operation when the first operation has generated the output.
Examiner’s Note:
Claim 13 of US Patent 12,189,564 teaches the bolded, underlined, and italicized limitations of Instant Claim 16.
Claim 14 of US Patent 12,189,564 teaches the bolded limitations of Instant Claim 16.
Claim 17: The method of claim 15, wherein the data processing system further comprises a compiler, further comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry.
Claim 15: The method of claim 13, wherein the data processing system further comprises a compiler, further comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, the recording unit, and the control unit.
Claim 18: The method of claim 17, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, the method further comprising: generating, with the compiler, in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements.
Claim 16: The method of claim 15, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, the method further comprising: generating, with the compiler, in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements.
Claim 19: The method of claim 17, wherein the data processing system further comprises runtime logic, and wherein configuring the reconfigurable processor further comprises: programming, with the runtime logic, the reconfigurable processor with the configuration data.
Claim 17: The method of claim 13, wherein the data processing system further comprises runtime logic, and wherein configuring the reconfigurable processor further comprises: programming, with the runtime logic, the reconfigurable processor with configuration data.
Claim 20: A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising: configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 18: A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor and external memory coupled to the reconfigurable processor, the instructions comprising: configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown, a second operation that receives the output of the first operation as an input, and control circuitry, comprising: a recording unit that generates control data that is indicative of the size of the output, and a control unit that fetches the control data from the recording unit and provides the control data to the second operation, wherein the control unit stores the control data in the external memory, wherein the second operation retrieves the control data from the external memory, and wherein the second operation processes the input based on the control data.
Claim 7: The data processing system of claim 1, wherein the reconfigurable processor is further configured to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 8: The data processing system of claim 7, wherein the reconfigurable processor is configured to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 18 of US Patent 12,189,564 teaches the bolded, underlined, and italicized limitations of Instant Claim 20.
Claim 7 of US Patent 12,189,564 teaches the bolded limitations of Instant Claim 20.
Claim 8 of US Patent 12,189,564 teaches the underlined limitations of Instant Claim 20.
Claim 1 of US Patent 12,189,564 teaches a data processing system that implements a first operation that generates an output with an unknown size and implements a second operation that receives the output of the first operation as an input, which claim 1 of the Instant Application also teaches. While claim 1 of US Patent 12,189,564 does not teach “wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuity, comprising: a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation” of instant claim 1, claims 7 and 8 of US Patent 12,189,564 of the same embodiment as claim 1 of US Patent 12,189,564 does disclose these limitations.
Independent claims 15 and 20 of Instant Application are similar to claim 1 of Instant Application and thus instant claim 15 is rejected under similar rationale in view of claims 7, 8, and 13 of US Patent 12,189,564 and instant claim 20 is rejected under similar rationale in view of claims 7, 8, and 18 of US Patent 12,189,564. While claim 15 of US Patent 12,189,564 is a method and claim 20 is a non-transitory medium, and claims 7 and 8 of US Patent 12,189,564 are a system, it would have been obvious for the method of claim 15 of US Patent 12,189,564 and the non-transitory medium of claim 20 of US Patent 12,189,564 to be implemented on an data processing system as disclosed in claims 7 and 8 of US Patent 12,189,564 to improve pipelined data operations in a data processing system.
Dependent claims 2-14 and 16-19 of Instant Application are rejected over claims 1-18 of US Patent 12,189,564. See Table Above.
Claims 1-20 are provisionally rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of copending Application No. 18/884,707 (reference application). Although the claims at issue are not identical, they are not patentably distinct from each other because claims 1-20 of US Application 18/884,707 disclose all of the features of claims 1-20 of the Instant Application.
As per claims 1-20,
Instant Application
US Application No. 18/884,707
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to: implement a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; implement a second operation that receives the output of the first operation as an input; and wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuity, comprising: a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor; and a compiler that generates configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input and control data that is indicative of the size of the output; and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements, and wherein the reconfigurable processor is configured with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 11: The data processing system of claim 8, wherein the reconfigurable processor is further configured with the configuration data to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 12: The data processing system of claim 11, wherein the reconfigurable processor is further configured with the configuration data to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 1 of US Application 18/884,707 teaches the bolded, underlined, and italicized limitations of Instant Claim 1.
Claim 11 of US Application 18/884,707 teaches the bolded limitations of Instant Claim 1.
Claim 12 of US Patent US Application 18/884,707 teaches the underlined limitations of Instant Claim 1.
Claim 2: The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units that implement the first and second operations.
Claim 2: The data processing system of claim 1, wherein the reconfigurable processor comprises arrays of coarse-grained reconfigurable (CGR) units that implement the first and second operations.
Claim 3: The data processing system of claim 1, wherein the control circuitry further comprises: a recording unit that generates control data that is indicative of the size of the output.
Claim 3: The data processing system of claim 1, wherein the compiler generates additional configuration data for configuring the reconfigurable processor to further implement control circuitry, wherein the control circuitry comprises a recording unit that generates the control data that is indicative of the size of the output, and wherein the reconfigurable processor is further configured with the additional configuration data such that the reconfigurable processor further implements the control circuitry.
Claim 4: The data processing system of claim 3, wherein the recording unit generates the control data while the first operation generates the output.
Claim 4: The data processing system of claim 3, wherein the recording unit generates the control data while the first operation generates the output.
Claim 5: The data processing system of claim 4, wherein the recording unit comprises: a counter that counts a number of elements in the output to generate the control data.
Claim 5: The data processing system of claim 3, wherein the recording unit comprises: a counter that counts a number of elements in the output to generate the control data.
Claim 6: The data processing system of claim 5, wherein the counter increments conditionally based on a predicate of the first operation.
Claim 6: The data processing system of claim 5, wherein the counter increments conditionally based on a predicate of the first operation.
Claim 7: The data processing system of claim 3, wherein the control unit fetches the control data from the recording unit.
Claim 8: The data processing system of claim 3, wherein the control circuitry further comprises a control unit that fetches the control data from the recording unit.
Claim 8: The data processing system of claim 7, wherein the control unit provides the control data to the second operation, wherein the second operation processes the input based on the control data.
Claim 9: The data processing system of claim 8, wherein the control unit provides the control data to the second operation, and wherein the second operation processes the input based on the control data.
Claim 9: The data processing system of claim 7, further comprising: external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 10: The data processing system of claim 8, further comprising: external memory that is coupled to the reconfigurable processor, wherein the control unit stores the control data in the external memory, and wherein the second operation retrieves the control data from the external memory.
Claim 10: The data processing system of claim 1, wherein the control circuitry further comprises: a synchronization unit that sends a signal to the second operation when the first operation has generated the output.
Claim 7: The data processing system of claim 3, wherein the control circuitry further comprises a synchronization unit that informs the second operation when the first operation has generated the output.
Claim 11: The data processing system of claim 10, wherein the reconfigurable processor is configured to enable the first operation to write, when the first operation has finished writing the first portion of the output and the second operation has finished reading the first portion of the input, a second portion of the output to the second portion of the buffer, while the second operation reads the first portion of the output from the first portion of the buffer as a second portion of the input.
Claim 13: The data processing system of claim 12, wherein the reconfigurable processor is further configured with the configuration data to enable the first operation to write, when the first operation has finished writing the first portion of the output and the second operation has finished reading the first portion of the input, a second portion of the output to the second portion of the buffer, while the second operation reads the first portion of the output from the first portion of the buffer as a second portion of the input.
Claim 12: The data processing system of claim 1, further comprising: a compiler that generates configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor; and a compiler that generates configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input and control data that is indicative of the size of the output; and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements, and wherein the reconfigurable processor is configured with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 3: The data processing system of claim 1, wherein the compiler generates additional configuration data for configuring the reconfigurable processor to further implement control circuitry, wherein the control circuitry comprises a recording unit that generates the control data that is indicative of the size of the output, and wherein the reconfigurable processor is further configured with the additional configuration data such that the reconfigurable processor further implements the control circuitry.
Claim 13: The data processing system of claim 12, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, and wherein the compiler generates in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor; and a compiler that generates configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input and control data that is indicative of the size of the output; and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements, and wherein the reconfigurable processor is configured with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 14: The data processing system of claim 1, further comprising: runtime logic that is configured to program the reconfigurable processor with configuration data such that the reconfigurable processor implements the first operation, the second operation, and the control circuitry.
Claim 1: A data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor; and a compiler that generates configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input and control data that is indicative of the size of the output; and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is suitable for a transmission of the predetermined maximum number of elements, and wherein the reconfigurable processor is configured with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 3: The data processing system of claim 1, wherein the compiler generates additional configuration data for configuring the reconfigurable processor to further implement control circuitry, wherein the control circuitry comprises a recording unit that generates the control data that is indicative of the size of the output, and wherein the reconfigurable processor is further configured with the additional configuration data such that the reconfigurable processor further implements the control circuitry.
Claim 14: The data processing system of claim 1, further comprising: runtime logic that receives the configuration data from the compiler and that is configured to program the reconfigurable processor with the configuration data.
Claim 15: A method of operating a data processing system that comprises a reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises: a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 15: A method of operating a data processing system that comprises a reconfigurable processor and a compiler, comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input, and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements; and configuring the reconfigurable processor with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 11: The data processing system of claim 8, wherein the reconfigurable processor is further configured with the configuration data to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 12: The data processing system of claim 11, wherein the reconfigurable processor is further configured with the configuration data to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 15 of US Application 18/884,707 teaches the bolded, underlined, and italicized limitations of Instant Claim 15.
Claim 11 of US Application 18/884,707 teaches the bolded limitations of Instant Claim 15.
Claim 12 of US Patent US Application 18/884,707 teaches the underlined limitations of Instant Claim 15.
Claim 16: The method of claim 15, further comprising: configuring the reconfigurable processor such that the control circuitry further comprises: a recording unit that generates control data that is indicative of the size of the output, wherein the control unit provides the control data to the second operation, and wherein the second operation processes the input based on the control data; and a synchronization unit that sends a signal to the second operation when the first operation has generated the output.
Claim 16: The method of claim 15, further comprising: generating, with the compiler, additional configuration data for configuring the reconfigurable processor to implement control circuitry, wherein the control circuitry comprises a synchronization unit that informs the second operation when the first operation has generated the output; and configuring the reconfigurable processor with the additional configuration data.
Claim 17: The method of claim 16, wherein the control circuitry further comprises a recording unit that generates control data that is indicative of the size of the output.
Claim 18: The method of claim 17, wherein the control circuitry further comprises a control unit that provides the control data to the second operation, wherein the second operation processes the input based on the control data.
Claim 17: The method of claim 15, wherein the data processing system further comprises a compiler, further comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement the first operation, the second operation, and the control circuitry.
Claim 15: A method of operating a data processing system that comprises a reconfigurable processor and a compiler, comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input, and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements; and configuring the reconfigurable processor with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 16: The method of claim 15, further comprising: generating, with the compiler, additional configuration data for configuring the reconfigurable processor to implement control circuitry, wherein the control circuitry comprises a synchronization unit that informs the second operation when the first operation has generated the output; and configuring the reconfigurable processor with the additional configuration data.
Claim 18: The method of claim 17, wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, the method further comprising: generating, with the compiler, in the configuration data a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements.
Claim 15: A method of operating a data processing system that comprises a reconfigurable processor and a compiler, comprising: generating, with the compiler, configuration data for configuring the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input, and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements; and configuring the reconfigurable processor with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 19: The method of claim 17, wherein the data processing system further comprises runtime logic, and wherein configuring the reconfigurable processor further comprises: programming, with the runtime logic, the reconfigurable processor with the configuration data.
Claim 19: The method of claim 15, wherein the data processing system further comprises runtime logic, and wherein configuring the reconfigurable processor further comprises: programming, with the runtime logic, the reconfigurable processor with the configuration data.
Claim 20: A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising: configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 20: A non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising: generating configuration data for the reconfigurable processor to implement: a first operation that generates an output, wherein a size of the output is unknown when generating the configuration data, and wherein the output comprises a number of elements that is smaller than or equal to a predetermined maximum number of elements, a second operation that receives the output of the first operation as an input, and a first connection for the output and a second connection for the input, wherein each one of the first and second connections is able to transport the predetermined maximum number of elements; and configuring the reconfigurable processor with the configuration data such that the reconfigurable processor implements the first operation, the second operation, the first connection, and the second connection.
Claim 11: The data processing system of claim 8, wherein the reconfigurable processor is further configured with the configuration data to store the output in a buffer during a write operation, and wherein the control unit directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claim 12: The data processing system of claim 11, wherein the reconfigurable processor is further configured with the configuration data to enable the first operation to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer.
Examiner’s Note:
Claim 20 of US Application 18/884,707 teaches the bolded, underlined, and italicized limitations of Instant Claim 20.
Claim 11 of US Application 18/884,707 teaches the bolded limitations of Instant Claim 20.
Claim 12 of US Patent US Application 18/884,707 teaches the underlined limitations of Instant Claim 20.
Claim 1 of US Application 18,884,707 teaches a data processing system that implements a first operation that generates an output with an unknown size and implements a second operation that receives the output of the first operation as an input, which claim 1 of the Instant Application also teaches. While claim 1 of US Application 18,884,707 does not teach “wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuity, comprising: a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation” of instant claim 1, claims 11 and 12 of US Application 18,884,707 of the same embodiment as claim 1 of US Application 18,884,707 does disclose these limitations.
Independent claims 15 and 20 of Instant Application are similar to claim 1 of Instant Application and thus instant claim 15 is rejected under similar rationale in view of claims 11, 12, and 15 of US Application 18,884,707 and instant claim 20 is rejected under similar rationale in view of claims 11, 12, and 20 of US Application 18,884,707. While claim 15 of US Application 18,884,707 is a method and claim 20 is a non-transitory medium, and claims 11 and 12 of US Application 18,884,707 are a system, it would have been obvious for the method of claim 15 of US Application 18,884,707 and the non-transitory medium of claim 20 of US Application 18,884,707 to be implemented on an data processing system as disclosed in claims 11 and 12 of US Application 18,884,707 to improve pipelined data operations in a data processing system.
Dependent claims 2-14 and 16-19 of Instant Application are rejected over claims 1-20 of US Application 18/884,707. See Table Above.
This is a provisional nonstatutory double patenting rejection because the patentably indistinct claims have not in fact been patented.
Allowable Subject Matter
Claims 1-20 would be allowable if rewritten or amended, or if a Terminal Disclaimer is filed, to overcome the rejection under Double Patenting, set forth in this Office action.
Regarding claim 1, none of the cited references either alone or in combination teaches a data processing system for implementing operations that generate a dynamically-sized output, comprising: a reconfigurable processor configured to: implement a first operation that generates an output, wherein a size of the output is unknown during a configuration phase; implement a second operation that receives the output of the first operation as an input; and wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer; and control circuity, comprising: a control unit that: directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Regarding claim 15, none of the cited references either alone or in combination teaches a method of operating a data processing system that comprises a reconfigurable processor, comprising: configuring the reconfigurable processor such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown during a configuration phase, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises: a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Regarding claim 20, none of the cited references either alone or in combination teaches a non-transitory computer-readable storage medium including instructions that, when executed by a processing unit, cause the processing unit to operate a data processing system that comprises a reconfigurable processor, the instructions comprising: configuring the reconfigurable processor with configuration data such that the reconfigurable processor implements: a first operation that generates an output, wherein a size of the output is unknown, a second operation that receives the output of the first operation as an input, a write operation that stores the output in a buffer, wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation.
Claims 2-14 and 16-19 are indicated as allowable subject matter because they are dependent on claims 1 and 15.
US PGPUB 2017/0177410 to Laroche discloses a processing pipeline that receives inputs and processes them in multiple processing task operations to generate multiple outputs stored in buffers. No mention of wherein, during a write operation, the first operation is enabled to write a first portion of the output to a first portion of a buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer is present.
US PGPUB 2017/0123794 to Chen discloses an array of processing elements that perform iteration processing of instructions. No mention of wherein the first operation is enabled to write a first portion of the output to a first portion of the buffer, while the second operation reads a first portion of the input that is different than the first portion of the output from a second portion of the buffer that is different than the first portion of the buffer, and control circuitry that comprises a control unit that directs the second operation during a read operation following the write operation to read data as the input from the buffer that was stored during the write operation is present.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2020/0348942 discloses multiple pipeline stages wherein each stage includes a corresponding buffer element.
US PGPUB 2014/0351526 discloses multiple write pipelines and multiple read pipelines, wherein each pipeline is associated with ingress and egress buffers.
US PGPUB 2004/0255088 discloses a read data buffer for storing data during a read operation and a write data buffer for storing data of a write operation that are both coupled in a sequential pipeline.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184