Prosecution Insights
Last updated: August 17, 2026
Application No. 18/884,842

HYBRID TEST READ SCHEME USING IN-NAND PARTIAL CHECKSUM

Non-Final OA §102
Filed
Sep 13, 2024
Examiner
PHAM, LY D
Art Unit
2827
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
SK hynix Inc.
OA Round
1 (Non-Final)
94%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 94% — above average
94%
Career Allowance Rate
975 granted / 1037 resolved
+26.0% vs TC avg
Minimal +3% lift
Without
With
+3.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 8m
Avg Prosecution
23 currently pending
Career history
1051
Total Applications
across all art units

Statute-Specific Performance

§101
8.3%
-31.7% vs TC avg
§103
23.9%
-16.1% vs TC avg
§102
39.0%
-1.0% vs TC avg
§112
12.2%
-27.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1037 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1 – 3, 7 – 9, 13, 16 and 17 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Wang et al. (US Pat pub 2025/0231873). Regarding claims 1, 7 and 13, Wang et al. disclose a memory device in a memory system (figs. 1 – 8), comprising: one or more super blocks (304 of fig. 3 or 400 of fig. 4), each super block including a plurality of memory blocks (304-1, 304-2, etc… in fig. 3; or blocks 402-1 – 402-n in fig. 4. See also para 0039); a control circuit in the memory device (302, fig. 3 or 404, fig. 4) and configured to perform a first test read on a codeword sequence from the plurality of memory blocks (see para 0003, 0020, etc…); and a partial checksum calculator in the memory device and configured to calculate a partial checksum on a syndrome sequence based on the codeword sequence and a subset matrix derived from a parity check matrix (see para 0020, 0026, 0036 and 0044, etc…), wherein the control circuit is configured to: compare the partial checksum with first and second thresholds (see para 0045, 0051); when it is determined that the partial checksum is less than the first threshold, determine that the codeword sequence is clean (para 0045, “checksum metric is below the threshold value”); when it is determined that the partial checksum is greater than the second threshold, determine that the codeword sequence is noisy (para 0046); and when it is determined that the partial checksum is in between the first threshold and the second threshold, perform by a controller of the memory system a second test read on the codeword sequence to determine a number of failed bit counts for the codeword sequence read from the plurality of memory blocks (referred to in para 0047 as “checksum metric is between the first threshold level and a second threshold level”. See further para 0051 – 0054). Regarding claims 2, 8 and 16, Want et al. also disclose the memory device of claim 1, wherein the control circuit is further configured to send the noisy codeword sequence to the controller for decoding and error correcting. (see para 0020, “perform error correction on the valid data using the ECC engine.…”. See also para 0026, 0028 and 0029, etc…). Regarding claims 3, 9, and 17, Wang et al. also disclose the memory device of claim 1, wherein the second threshold is greater than or equal to the first threshold (inherent because that’s the only way a situation in which the checksum is between the first threshold and the second threshold can occur). Allowable Subject Matter Claims 4 – 6, 10 – 12, 14, 15, and 18 – 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior arts of record fail to teach or reasonably suggest the memory and operating method as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 4, 6, 10, 12, 14, 18 and 20. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LY D. PHAM Examiner Art Unit 2827 /LY D PHAM/Primary Examiner, Art Unit 2827 July 24, 2026
Read full office action

Prosecution Timeline

Sep 13, 2024
Application Filed
Jul 13, 2026
Request for Continued Examination
Jul 16, 2026
Response after Non-Final Action
Jul 30, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12706138
DATA READ CIRCUIT AND STORAGE DEVICE THEREOF
1y 9m to grant Granted Aug 11, 2026
Patent 12700440
OFFSET CANCELLATION
2y 1m to grant Granted Aug 04, 2026
Patent 12694916
NONVOLATILE MEMORY DEVICE, METHOD OF CONTROLLING INITIALIZATION OF NONVOLATILE MEMORY DEVICE, AND STORAGE DEVICE
1y 10m to grant Granted Jul 28, 2026
Patent 12688884
VARIABLE WIDTH MEMORY MODULE SUPPORTING ENHANCED ERROR DETECTION AND CORRECTION
2y 3m to grant Granted Jul 21, 2026
Patent 12685232
STACKED SEMICONDUCTOR DEVICE
2y 0m to grant Granted Jul 14, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

Strategy Recommendation AI-generated — please review before filing

Get a prosecution strategy drawn from examiner precedents, rejection analysis, and claim mapping.
Typically takes 5-10 seconds — AI-generated, attorney review required before filing

Prosecution Projections

1-2
Expected OA Rounds
94%
Grant Probability
97%
With Interview (+3.3%)
1y 8m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1037 resolved cases by this examiner. Grant probability derived from career allowance rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month