DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1 – 3, 5, 7 – 13, 15, and 17 – 19 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chung et al. (US 12,389,660).
Regarding claim 1, Chung teaches (FIG. 2):
A semiconductor structure, comprising:
a substrate (261);
a source/drain (S/D) structure comprising a lower S/D portion disposed above the substrate and an upper S/D portion disposed above the lower S/D portion, the lower S/D portion comprising a high temperature silicide structure (205) and an etch stop material structure (203) surrounding at least a portion of the high temperature silicide structure, the upper S/D portion comprising an epitaxial (EPI) material (230) in contact with the high temperature silicide structure; and
a backside metal structure (250/209/245) that extends through the substrate and is in contact with the high temperature silicide structure.
Regarding claim 2, Chung teaches (col 8, line 56 – 66):
The semiconductor structure of claim 1, wherein the high temperature silicide structure comprises a structure having an annealing temperature of at least 350 degrees Celsius.
Regarding claim 3, Chung teaches (col 8, line 56 – 66):
The semiconductor structure of claim 1, wherein the high temperature silicide structure comprises a structure having an annealing temperature of at least 750 degrees Celsius.
Regarding claim 5, Chung teaches (FIG. 2):
The semiconductor structure of claim 1, wherein the backside metal structure is in contact with a bottom surface of the high temperature silicide structure.
Regarding claim 7, Chung teaches (col 11, line 25 – 30):
The semiconductor structure of claim 1, wherein the etch stop material comprises at least one of silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), aluminum nitride (AlN), or an area-selective deposition (ASD) dielectric.
Regarding claim 8, Chung teaches (col 9, line 12 – 16):
The semiconductor structure of claim 1, wherein the high temperature silicide structure comprises at least one of titanium (Ti), cobalt (Co), or nickel (Ni).
Regarding claim 9, Chung teaches (FIG. 3A – 3Q):
A method for fabricating a semiconductor structure, the method comprising:
providing a substrate (261);
forming, above the substrate, a lower portion of a source/drain (S/D) structure comprising a high temperature silicide structure (205) and an etch stop material structure (207) that surrounds at least a portion of the high temperature silicide structure;
forming, above the lower portion of the S/D structure, an upper portion of the S/D structure comprising an epitaxial (EPI) material (230) that is in contact with the high temperature silicide structure; and
forming a backside metal structure (250/209/245) that extends through the substrate and is in contact with the high temperature silicide structure.
Regarding claim 10, Chung teaches (FIG. 3A – 3Q):
The method of claim 9, wherein forming the lower portion of the S/D structure comprises:
forming the etch stop material structure;
depositing the high temperature silicide structure above the etch stop material structure; and
annealing the high temperature silicide structure.
Regarding claim 11, Chung teaches (col 8, line 56 – 66):
The method of claim 10, wherein annealing the high temperature silicide structure comprises annealing the high temperature silicide structure at a temperature of at least 350 degrees Celsius.
Regarding claim 12, Chung teaches (col 8, line 56 – 66):
The method of claim 10, wherein annealing the high temperature silicide structure comprises annealing the high temperature silicide structure at a temperature of at least 750 degrees Celsius.
Regarding claim 13, Chung teaches (col 11, line 25 – 30):
The method of claim 10, wherein forming the etch stop material structure comprises forming the etch stop material from at least one of silicon carbon nitride (SiCN), silicon carbon oxynitride (SiCON), aluminum nitride (AlN), or an area-selective deposition (ASD) dielectric.
Regarding claim 15, Chung teaches (FIG. 3H – 3Q):
The method of claim 9, wherein forming the backside metal structure that extends through the substrate and is in contact with the high temperature silicide structure comprises:
etching the substrate to expose the etch stop material;
etching the etch stop material to expose at least a bottom surface of the high temperature silicide structure; and
depositing metal onto the least the bottom surface of the high temperature silicide structure to form the backside metal structure.
Regarding claim 17, Chung teaches (col 6, line 2 – 10):
The method of claim 9, wherein forming the backside metal structure comprises forming a copper structure.
Regarding claim 18, Chung teaches (col 9, line 12 – 16):
The method of claim 9, wherein the high temperature silicide structure comprises at least one of titanium (Ti), cobalt (Co), or nickel (Ni).
Regarding claim 19, Chung teaches (FIG. 2):
An apparatus, comprising:
a field effect transistor (FET) structure, wherein the FET structure comprises:
a substrate (261);
a gate structure (215), disposed above the substrate and comprising a vertical metal gate structure and a channel structure (21), the channel structure comprising a plurality of vertically-stacked channels extending horizontally through the vertical metal gate structure (FIG. 2);
a source/drain (S/D) structure, comprising a lower S/D portion, disposed above the substrate, comprising a high temperature silicide structure (205) and an etch stop material structure (203) surrounding at least a portion of the high temperature silicide structure, and further comprising an upper S/D portion (230), disposed above the lower S/D portion, comprising an epitaxial (EPI) material in contact with a first end of each vertically-stacked channel of the plurality of vertically-stacked channels (FIG. 2); and
a backside metal structure (250/209/245) that extends through the substrate and is in contact with the high temperature silicide structure.
Allowable Subject Matter
Claims 4, 6, 14, 16, and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 4, 14, and 20, the prior art of record fails to teach or fairly render obvious a frontside high temperature silicide contact structure extending through the EPI material of the upper S/D portion into the high temperature silicide structure of the lower S/D portion, in combination with the other limitations of the claims.
Regarding claims 6 and 16, the prior art of record fails to teach or fairly render obvious wherein the backside metal structure is further in contact with a side surface of the high temperature silicide structure, in combination with the other limitations of the claims.
Chung teaches a frontside silicide formed in a similar manner to the backside silicide, however Chung does not teach extending the frontside silicide layer through the epitaxial layer and into the backside silicide.
Lin et al. (US 2022/0165848) teaches a source/drain contact extending from front to back, however the contact is not formed from high temperature silicide.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CORY W ESKRIDGE whose telephone number is (571)272-0543. The examiner can normally be reached M - F 9 - 5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio Madonado can be reached at 571-272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/CORY W ESKRIDGE/Primary Examiner, Art Unit 2898
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