DETAILED ACTION
1. This Office Action is responsive to the application filed on July 25, 2024. Claims 1-20 are pending.
Information Material to Patentability
2. Applicant is reminded of the continuing obligation under 37 CFR 1.56, to timely apprise the Office of any information which is mate-rial to patentability of the claims under consideration in this reissue appli-cation.
These obligations rest with each individual associated with the filing and prosecution of this application for reissue. See also MPEP §§ 1404, 1442.01 and 1442.04.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
5. Claims 1, 3-6, 8, 10-13, 15, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2022/0392503 (“Chang”).
6. With respect to claim 1, Chang discloses a method of operating a memory device, the method comprising:
receiving a Column Address Strobe (CAS) command from a memory controller (paragraph [0076], “The SoC 200a may issue a CAS command to the DRAM 100a in synchronization with WCK2CK.”);
receiving a first command from the memory controller after a first time period from a time point at which the CAS command is received (paragraph [0076], “The DRAM 100a may start DCM by setting mode register MR in response to the CAS command. The DCM may perform first training on the write path during a first training period tDCMM/2 and perform and perform second training on the read path during a second training period tDCMM/2.”; write path training requires a write command and setting register requires MRW command);
performing an offset calibration training operation based on the first command (paragraph [0076], “The DRAM 100a may compensate for the duty according to the first DCA code value in the write mode and compensate for the duty according to the second DCA code value in the read mode.”);
receiving a second command after a second time period from a time point at which the first command is received (read path training requires a read command which is received after the write command; see also paragraph [0051], storing MCM result for the read path requires MRW command); and
terminating the offset calibration training operation based on the second command (completion of read path training, which is based on the read command, terminated the training).
7. With respect to claims 8 and 15, see the rejection of claim 1 above.
8. With respect to claim 3, Chang discloses the method of claim 1, wherein the first command is a first Mode Register Write (MRW) command for starting the offset calibration training operation, and wherein the second command is a second MRW command for ending the offset calibration training operation (see the rejection of claim 1 above).
9. With respect to claim 4, Chang discloses the method of claim 3, wherein the first MRW command includes one or more first MRW commands, and wherein the second MRW command includes one or more second MRW commands (see the rejection of claim 1 above).
10. With respect to claim 5, Chang discloses the method of claim 1, further comprising: receiving a data clock signal from the memory controller (FIG. 5, S111), wherein the first time period includes a third time period for start driving the data clock signal, and a fourth time period for adjusting the data clock signal to toggle at a predetermined rate (see FIG. 5).
11. With respect to claim 6, Chang discloses the method of claim 5, further comprising: receiving a third command after a fifth time period (any command received after the fifth time period, for example a read command) from a time point at which the second command is received, wherein the data clock signal is not received from the memory controller after the fifth time period based on the third command (data clock received during a write command after the fifth time period is not based on a read command).
12. With respect to claims 10-13, 17-18, and 20, see the rejection of claims 3-6 above, respectively.
13. Claims 1, 3-8, 10-15, and 17-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2023/0005515 (“Kim”).
14. With respect to claim 1, Kim discloses a method of operating a memory device, the method comprising:
receiving a Column Address Strobe (CAS) command from a memory controller (paragraphs [0036] and [0038], Kim discloses read and write commands which require RAS and CAS to latch an address for a read or write command; read or write operation performed prior a training operation teaches this limitation);
receiving a first command from the memory controller after a first time period from a time point at which the CAS command is received (FIG 10, MRW-1/MRW-2 to start MRW-DCM Start);
performing an offset calibration training operation based on the first command (see FIG. 9);
receiving a second command after a second time period from a time point at which the first command is received (FIG. 10, third set of MRW-1/MRW2 to stop MRW-DCM); and
terminating the offset calibration training operation based on the second command (see FIG. 10).
15. With respect to claims 8 and 15, see the rejection of claim 1 above.
16. With respect to claim 3, Kim discloses the method of claim 1, wherein the first command is a first Mode Register Write (MRW) command for starting the offset calibration training operation, and wherein the second command is a second MRW command for ending the offset calibration training operation (see FIG. 10 and the rejection of claim 1 above).
17. With respect to claim 4, Kim discloses the method of claim 3, wherein the first MRW command includes one or more first MRW commands, and wherein the second MRW command includes one or more second MRW commands (see FIG. 10 and the rejection of claim 1 above).
18. With respect to claim 5, Kim discloses the method of claim 1, further comprising: receiving a data clock signal (FIG. 10, WCK) from the memory controller, wherein the first time period includes a third time period for start driving the data clock signal, and a fourth time period for adjusting the data clock signal to toggle at a predetermined rate (see FIGs. 6-8).
19. With respect to claim 6, Kim discloses the method of claim 5, further comprising: receiving a third command after a fifth time period (any command received after the fifth time period, for example a read command) from a time point at which the second command is received, wherein the data clock signal is not received from the memory controller after the fifth time period based on the third command (data clock received during a write command after the fifth time period is not based on a read command).
20. Claims 1-2, 8-9, 15-16 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Pub. 2018/0167055 (“Gans”).
21. With respect to claim 1, Gans discloses a method of operating a memory device, the method comprising:
receiving a Column Address Strobe (CAS) command from a memory controller (FIG. 11, CAS at T0);
receiving a first command from the memory controller after a first time period from a time point at which the CAS command is received (FIG 11, WR at T1);
performing an offset calibration training operation based on the first command (see paragraph [0096]);
receiving a second command after a second time period from a time point at which the first command is received (see paragraph [0096], calibration command); and
terminating the offset calibration training operation based on the second command (termination of calibration is based on the calibration command).
22. With respect to claims 8 and 15, see the rejection of claim 1 above.
23. With respect to claim 2, Gans disclose the method of claim 1, wherein the performing of the offset calibration training operation includes:
enabling an on-die termination (ODT) circuit of the memory device, and
adjusting ODT resistance code input to the ODT circuit, the ODT resistance code being provided by an offset calibration circuit of the memory device (see FIG. 9 and paragraphs [0075] and [0097]).
24. With respect to claims 9 and 16, see the rejection of claim 2 above.
Allowable Subject Matter
25. Claims 7, 14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: when considered in combination with all of the other limitations of the claims, the prior art of record does not teach or suggest “the method of claim 1, wherein the second time period includes a time period for performing the offset calibration training operation, and wherein the second time period does not exceed 3 μs (micro seconds)”.
Conclusion
26. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Woo H Choi whose telephone number is (571)272-4179. The examiner can normally be reached 9 am - 5 pm.
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/Woo H Choi/
Primary Examiner,
Art Unit 3992