Prosecution Insights
Last updated: October 04, 2026
Application No. 18/885,513

CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES, AND METHODS OF FABRICATION

Non-Final OA §112
Filed
Sep 13, 2024
Priority
May 12, 2014 — reissue of 9402312
Examiner
HUGHES, DEANDRA M
Art Unit
3992
Tech Center
3900
Assignee
Adeia Semiconductor Technologies LLC
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
150 granted / 191 resolved
+18.5% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
22 currently pending
Career history
205
Total Applications
across all art units

Statute-Specific Performance

§101
3.4%
-36.6% vs TC avg
§103
15.8%
-24.2% vs TC avg
§102
8.4%
-31.6% vs TC avg
§112
26.9%
-13.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 191 resolved cases

Office Action

§112
NON-FINAL OFFICE ACTION Acknowledgements 1. This non-final Office Action addresses reissue U.S. Application No. 18/885,513 (“instant application”). Examiners find the actual filing date of the instant application is Sept. 13, 2025. 2. The instant application is a reissue application of U.S. Patent No. 9,402,312, (“‘312 Patent”) issued Jul. 26, 2016. The ‘312 Patent was filed on May 12, 2014 as U.S. Application No. 14/275,741 (“741 Application”), titled “CIRCUIT ASSEMBLIES WITH MULTIPLE INTERPOSER SUBSTRATES AND METHODS OF FABRICATION”. 3. Examiners do not find any certificates of correction, ongoing/previous proceedings before the Office, or current ongoing litigation involving the ‘312 Patent. 4. The ‘312 Patent issued with claims 1-16 (“Patented Claims”). In the preliminary amendment filed Sept. 13, 2024 ("SEPTEMBER 2024 CLAIM AMENDMENTS"), claims 17-24 are added. 5. Claims 1-24 are pending and examined and are grouped as follows: claims 1-4; claims 5-8; claims 9-10; claims 11-12; claims 13-14; claims 15-24. Priority Claims 6. Examiners find the instant application does not claim domestic priority under 35 U.S.C. § 120 or 35 U.S.C. § 119(e). 7. Examiners find the instant application does not claim foreign priority. 8. The presumed effective U.S. filing date of the instant application is May 12, 2014. Objection to the Specification 9. The amendment to the specification filed Sept. 13, 2024 is objected to because it does not comply with the marking requirements of 37 CFR §1.173. Specifically, the matter added to the patent must be underlined. CORRECTION IS REQUIRED. Claim Rejections - 35 USC § 112 10. Claims 1-12 and 15-24 are rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Specifically, the claim phrase “wherein the 1st circuit layer comprises 1st contact pads on top” is indefinite because it is unclear whether the “contact pads” are located on the top of the “1st circuit layer” or alternatively on top of one of the other claimed layers, e.g., the “constituent circuit layer.” Allowable Subject Matter 11. Claims 13-14 are allowed and if the §112(b) rejections are overcome, then claims 1-12 and 15-24 would be in condition for allowance. As to claim 1, the prior art does not disclose or make obvious “wherein the circuit assembly further comprises one or more circuit modules at least one of which comprises an integrated circuit, the one or more circuit modules overlying the 1st circuit layer, each circuit module comprising one or more contact pads attached to one or more 1st contact pads; wherein at least a portion of at least one 1st contact pad overlies a gap separating at least two of the adjacent substrates from each other“ in combination with the other limitations of the claims. As to claim 5, the prior art does not disclose or make obvious “wherein for each of one or more of the constituent interposers, the constituent interposer comprises a 2nd constituent circuit layer which is part of the 2nd circuit layer, the 2nd constituent circuit layer being present on a bottom surface of the constituent interposer's substrate, the 2nd constituent circuit layer comprising circuitry; wherein the 2nd circuit layer comprises each 2nd constituent circuit layer; wherein the 2nd circuit layer comprises 2nd contact pads on the bottom; wherein one or more of the constituent interposers each comprise one or more conductive through-paths passing through the constituent interposers' substrates, each conductive through-path being connected to at least one 1st constituent circuit layer and at least one 2nd constituent circuit layer“ in combination with the other limitations of the claims. As to claim 9, the prior art does not disclose or make obvious “wherein the combined interposer comprises a 1st circuit layer comprising a circuitry, wherein the 1st circuit layer comprises a redistribution layer including a dielectric layer deposited over one or more of the substrates and a conductor embedded in the dielectric layer, wherein at least a portion of the 1st circuit layer is physically contacting a top surface of one or more of the substrates“ in combination with the other limitations of the claims. As to claim 11, the prior art does not disclose or make obvious “wherein for each of one or more of the constituent interposers, the constituent interposer comprises a 2nd constituent circuit layer which is part of the 2nd circuit layer, the 2nd constituent circuit layer being present on a bottom surface of the constituent interposer's substrate, the 2nd constituent circuit layer comprising circuitry; wherein the 2nd circuit layer comprises each 2nd constituent circuit layer; wherein the 2nd circuit layer comprises 2nd contact pads on the bottom; wherein one or more of the constituent interposers each comprise one or more conductive through-paths passing through the constituent interposers' substrates, each conductive through-path being connected to at least one 1st constituent circuit layer and at least one 2nd constituent circuit layer“ in combination with the other limitations of the claims. As to claim 15, the prior art does not disclose or make obvious “wherein the combined interposer further comprises 2nd contact pads on the bottom, and comprises one or more circuits each of which passes through a gap between adjacent ones of the substrates from a region above the substrates to a region below the substrates and is connected to one or more 1st contact pads and to one or more 2nd contact pads“ in combination with the other limitations of the claims. Conclusion 12. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DEANDRA M HUGHES whose telephone number is (571)272-6982. The examiner can normally be reached Generally M-Th 8AM-6PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hetul Patel can be reached at 571-272-4184. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Signed: /DEANDRA M HUGHES/Reexamination Specialist, Art Unit 3992 Conferees: /CHRISTINA Y. LEUNG/Primary Examiner, Art Unit 3991 /H.B.P/ Hetul PatelSupervisory Patent Examiner, Art Unit 3992
Read full office action

Prosecution Timeline

Sep 13, 2024
Application Filed
Sep 13, 2024
Response after Non-Final Action
Aug 18, 2026
Non-Final Rejection mailed — §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
97%
With Interview (+18.4%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 191 resolved cases by this examiner. Grant probability derived from career allowance rate.

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