Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested:
MEMORY DIE ARRANGEMENT IN A SEMICONDUCTOR PACKAGE
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [US PGPUB 20140126274] in view of Ishino et al. [US PGPUB 20060267188] (hereinafter Lee and Ishino).
Regarding claim 1, Lee teaches a semiconductor package comprising:
a logic die (430, Para 27) having a first planar area (Fig. 4C –i.e., top surface of 430);
a cache memory die (420, Para 27) on the logic die (Fig. 4C), the cache memory die having the first planar area (Fig. 4C –i.e., top surface of 420);
a main memory die stack structure (Para 27, group of 4 die 410) on the cache memory die (Fig. 4C), the main memory die stack structure including main memory dies stacked in a vertical direction and having a second planar area smaller than the first planar area (Fig. 4C).
Lee does not specifically disclose a mold on the cache memory die, the mold covering sidewalls of the main memory dies.
However, it is noted that Lee details the structure of stack 410 (Fig. 5B), wherein the memory dies of the stack are spaced.
Referring to the invention of Ishino, Ishino teaches providing mold material 50 or 50/52 (Para 87; wherein material 50/52 together are structurally capable of being referred to as “mold”) to fill gaps between stacked chips of the device, wherein in providing the mold material, the mold material is also provided on the sidewalls of the stacked chips of the device.
In view of such teaching by Ishino, it would have been obvious to a person having ordinary skills in the art before the effective filing date of the claimed invention to have the invention of Lee comprise the teaching of Ishino, to help provide structural integrity to the device and/or prevent the components from moisture (Para 24, Fig. 1).
Thus, if the mold is interpreted to be material 50 as taught by Ishino, then the mold applied in Lee’s invention would result in the mold being at least between the main memory dies 410, cover the sidewall of the main memory dies, and be on the cache memory die (which is structurally similar to interposer chip 40 of Ishino). And if the mold is interpreted to be material 50/52, the mold would obviously be on the entire structure of Lee except the uppermost surface of main memory die and the bottom surface of the logic die.
Allowable Subject Matter
Claims 12-20 are allowed.
Claims 2-11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claims 12-20 are allowed because all prior arts of record and related prior arts not of record either singularly or in combination fail to anticipate or render obvious a semiconductor package comprising:
an inactive element on the cache memory die, the inactive element being spaced apart from the main memory die stack structure in a horizontal direction; and (as claimed in claim 12 and 18), in combination with the rest of claim limitations as claimed and defined by the Applicant.
Conclusion
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/ISMAIL A MUSE/ Primary Examiner, Art Unit 2812
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