DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to the Applicant’s communication filed on September 16, 2024. In virtue of this communication, claims 1-16 are currently presented in the instant application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
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Claims 1, 3-8 and 10-16 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1, 4-6, 8, 10, 12-13, 16-17 and 19 of U.S. Patent No. 12,120,790.
Although the claims at issue are not identical, they are not patentably distinct from each other because the above indicated claims of the instant application are either anticipated by, or would have been obvious over, the above identified claims of the above patent, including:
As claim 1: A circuit, comprising: a single-output voltage converter having a converter output and first and second converter inputs, wherein the first converter input is coupled to a power supply input, and the second converter input is coupled to a ground terminal; a buck regulator having first and second buck inputs and a buck output, wherein the first buck input is coupled to the converter output, and the second buck input is coupled to the second converter input; first and second LED input terminals, wherein the first LED input terminal is coupled to the converter output, and the second LED input terminal is coupled to the buck output; and third and fourth LED input terminals, wherein the third LED input terminal is coupled to the converter output, and the fourth LED input terminal is coupled to the second converter input and the ground terminal (see claim 12 of the above patent).
As claim 3: The circuit of claim 1, wherein the buck regulator is configured to provide a first voltage to the second LED input terminal, and the single-output voltage converter is configured to provide a second voltage to the third LED input terminal (see claims 4 and 12 of the above patent).
As claim 4: The circuit of claim 3, wherein the second voltage is greater than the first voltage (see claim 5 of the above patent).
As claim 5: The circuit of claim 1, wherein the buck regulator is configured to sink current from the second LED input terminal (see claim 16 of the above patent).
As claim 6: The circuit of claim 1, wherein the buck regulator is a synchronous buck regulator (see claim 19 of the above patent).
As claim 7: The circuit of claim 1, wherein the power supply input is configured to receive an alternating current (AC) signal (see claims 1, 8 or 12 of the above patent).
As claim 8: A system, comprising: a single-output voltage converter having a converter output and first and second converter inputs, wherein the first converter input is configurable to receive an alternating current (AC) power signal, and the second converter input is coupled to a ground terminal; a buck regulator having first and second buck inputs and a buck output, wherein the first buck input is coupled to the converter output, and the second buck input is coupled to the second converter input and the ground terminal; first and second LED input terminals, wherein the first LED input terminal is coupled to the buck output, and the second LED input terminal is coupled to the ground terminal; and third and fourth LED input terminals, wherein the third LED input terminal is coupled to the converter output, and the fourth LED input terminal is coupled to the second converter input and the ground terminal (see claim 12 of the above patent).
As claim 10: The system of claim 8, wherein the buck regulator is configured to source current to the first LED input terminal (see claim 10 of the above patent).
As claim 11: The system of claim 8, wherein the buck regulator is a synchronous buck regulator (see claim 19 of the above patent).
As claim 12: A circuit, comprising: a single-output voltage converter having a converter output and first and second converter inputs, wherein the second converter input is coupled to a ground terminal, and the single-output voltage converter is configured to provide a first voltage at the converter output; a buck regulator having first and second buck inputs and a buck output, wherein the first buck input is coupled to the converter output, the second buck input is coupled to the second converter input, and the buck regulator is configured to provide a second voltage at the buck output; first and second load terminals, wherein the first load terminal is coupled to the converter output, and the second load terminal is coupled to the second buck input and the ground terminal; and third and fourth load terminals, wherein the third load terminal is coupled to the converter output, and the fourth load terminal is coupled to the buck output (see claim 12 of the above patent).
As claim 13: The circuit of claim 12, wherein the first load terminal is coupled to the third load terminal (see claim 13 of the above patent).
As claim 14: The circuit of claim 12, wherein the buck regulator is configured to sink current from the third load terminal (see claims 6 and 16 of the above patent).
As claim 15: The circuit of claim 12, wherein the buck regulator is configured to source current to the third load terminal (see claims 10 and 17 of the above patent).
As claim 16: The circuit of claim 12, wherein the buck regulator is a synchronous buck regulator (see claim 19 of the above patent).
Allowable Subject Matter
Claims 2 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Prior art of record fails to disclose or fairly suggest the following limitations:
A circuit, comprising … “further comprising fifth and sixth LED input terminals, wherein the fifth LED input terminal is coupled to the converter output, and the sixth LED input terminal is coupled to the second converter input and the ground terminal”, as claimed in dependent claims 2 and 9.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Prior art Yang et al. – US 7,675,240
Prior art Maisel et al. – US 6,265,832
Prior art Chen et al. – US 2010/0148679
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/TUNG X LE/Primary Examiner, Art Unit 2844 December 9, 2025