Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 6/8/2026. The changes and remarks disclosed therein have been considered. Claims 1-3, 9-13, 15, 18-19 have been amended. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-9, 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh PG PUB 20220293174 (hereinafter Khaddam), in view of Le Gallo-Bourdeau PG PUB 20240160348 (hereinafter Le Gallo).
Regarding independent claim 1, Khaddam teaches a non-volatile memory (title of Khaddam), comprising:
a first memory area (a group of memory cells storing neural-network weights that participate in the first computation, e.g., one array, one blocks of row/columns, one layer’s weight matrix) comprising a first plurality of storage elements (e.g., resistive memory cells) configured to store weight values (e.g., conductance value) associated with a first plurality of neurons of a neural network ([0021] of Khaddam, “…A fundamental computational primitive is a matrix-vector multiplication…”, [0036] of Khaddam, “…matrix multiplication uses Ohm's law and Kirchhoff s law in a resistive memory crossbar array…”, since the conductance values of the memory elements represent weights in the matrix, Khaddam teaches storage elements storing neural-network weight value);
a second memory area (another group of memory cells, separate from the first one, Khaddam teaches multiple arrays/crossbar structures that store weight matrices, these arrays inherently form separate groups of memory cells corresponding to different neural network layers) comprising a second plurality of storage elements (Khaddam teaches crossbar arrays containing multiple resistive memory cells arranged at intersection of row and columns, [0002] of Khaddam, “…The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element…”);
a control circuit ([0033] of Khaddam, “…device 100 further comprises control circuitry 13 configured to control the signal generator 11 and the readout circuit 12…”), configured to apply one or more first input values to a plurality of first read paths, each first read path comprising one storage element among the first plurality of storage elements, first read current at each first read path based on at least one of the one or more first input values ([0032] of Khaddam, “…device is further configured to read out current values of columns of the memory array. The current values represent result values of vector elements of a result vector of the multiplication…”, thus the control circuitry applies signals that create read paths through memory cells, currents generated in the crossbar depend on the input voltages and conductance values, the amendments merely identify the currents associated with the first read paths as “first read currents” and do not patentably distinguish over the applied references);
a first computing circuit configured to add first read currents generated by the first read paths to generate a first output current ([0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203….is the sum of three multiplications…”, Khaddam teaches adding read currents to generate an output current representing neural-network computation); and
But Khaddam does not teach a programming circuit configured to convert the first output current into a first programming current, and to use said first programming current to program a first storage element of the second plurality of storage elements, in particular, Khaddam does not explicitly teach converting the output current into a programming current used to program another storage element.
However, Le Gallo teaches programming memory elements in an in-memory computing device using programming signals to adjust conductance values ([0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”). Le Gallo further teaches adjusting conductance values of memory elements to match target value ([0047] of Le Gallo, “…memory elements are adjusted …to match the summed conductance of the K memory elements of the cell with the target conductance value…”). The claims do no specify any particular circuitry for converting the output current into the programming current. Accordingly, the claimed programming currently broadly encompasses programming currents generated by conventional programming circuitry.
Khaddam teaches a compute-in-memory neural network architecture implemented using non-volatile resistive memory crossbar arrays storing synaptic weights and generating output currents by summing read current. However, Khaddam does not explicitly teach converting the output current into a programming current to program another storage elements. Le Gallo teaches programming memory elements of an in-memory computing device by applying programming signals to adjust conductance values. It would have been obvious to incorporate the programming techniques of Le Gallo into neural network architecture of Khaddam to enable updating weight stored in the crossbar memory cells. Le Gallo explains that adjusting conductance values of memory elements allows programming weight in in-memory-computing devices. Applying such programming techniques to the crossbar architecture of Khaddam would improve functionality by allowing training and adjustment of stored weight.
Regarding claim 2, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1:
wherein the control circuit ([0033] of Khaddam, “…device 100 further comprises control circuitry 13 configured to control the signal generator 11 and the readout circuit 12…”) is further configured to apply, to a plurality of second read paths (e.g., read path through second memory area), one or more second input values generated by reading the first storage element of the second plurality of storage elements (Khaddam teaches applying signals to memory crossbar lines and reading resulting currents, [0032] of Khaddam, “…device is further configured to read out current values of columns of the memory array. The current values represent result values of vector elements of a result vector of the multiplication…”),
each second read path (e.g., read path through second memory area) comprising one storage element among the second plurality of storage elements second read current at each second read path (Khaddam teaches applying signals to memory crossbar lines and reading resulting currents, [0032] of Khaddam, “…device is further configured to read out current values of columns of the memory array. The current values represent result values of vector elements of a result vector of the multiplication…”); and further comprising a second computing circuit configured to add second read currents generated by the second read paths to generate a second output current ([0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203….is the sum of three multiplications…”, Khaddam teaches adding read currents to generate an output current representing neural-network computation);
wherein the programming circuit is configured to convert the second output current into a second programming current, and to use said second programming current to program another storage element of the first memory area ([0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”)
Regarding claim 3, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 2: wherein the control circuit ([0033] of Khaddam, “…device 100 further comprises control circuitry 13 configured to control the signal generator 11 and the readout circuit 12…”, Khaddam teaches neural network computation uses multiple input vectors applied to crossbar rows) is further configured (repeating same read-compute-program procedure using another read path set associated with another storage element group, neural networks inherently support multiple input vectors) to apply, to a plurality of third read paths (e.g., read path through third memory area), one or more third input values generated by reading the another storage element of the first memory area (Khaddam teaches applying signals to memory crossbar lines and reading resulting currents, [0032] of Khaddam, “…device is further configured to read out current values of columns of the memory array. The current values represent result values of vector elements of a result vector of the multiplication…”), each third read path comprising one storage element among the first plurality of storage elements third read current at each third read path; and wherein the first computing circuit is further configured to add currents generated by the third read paths to generate a third output current ([0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203….is the sum of three multiplications…”, Khaddam teaches adding read currents to generate an output current representing neural-network computation); and wherein the programming circuit is further configured to convert the third output current into a third programming current, and to reprogram the first storage element of the second plurality of storage elements by using said third programming current ([0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”)
Regarding claim 4, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 3, wherein the storage elements comprised in the first read paths define weights associated with an input layer of the neural network and wherein the storage elements comprised in the third read paths define weights associated with another layer of the neural network (Khaddam teaches storage of neural network weights in crossbar memory cells, [0021] of Khaddam, “…A fundamental computational primitive is a matrix-vector multiplication…”, thus the memory cells correspond to neural weights).
Regarding claim 5, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 4, wherein the another layer is an output layer (Khaddam teaches neural network matrices represent connections between layers including output layers, [0021] of Khaddam, “…A fundamental computational primitive is a matrix-vector multiplication…”, thus Khaddam inherently teaches neural network layers).
Regarding claim 6, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein the weight values stored by the first plurality of storage elements define weights of neurons belonging to layers of one parity of the neural network and the weights stored by the second plurality of storage elements define weights of neurons belonging to layers of another parity of the neural network (Partitioning weights into groups for error detection and reliability is a conventional memory design practice, it would have been an obvious implementation choice for memory organization and neural network architecture. Crossbar arrays store weights in structured matrices, [0002] of Khaddam, “…the device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element…”).
Regarding claim 7, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 6, wherein said one parity is odd parity and said another parity is even parity (Parity organization is a conventional memory reliability technique and would have been obvious to apply to stored weight values).
Regarding claim 8, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein each storage element, among the first and the second plurality of storage elements, belongs to a memory cell, each memory cell being coupled to the control circuit via a word line and bit line, the control circuit being configured to activate or deactivate word lines and bit lines ([0002] of Khaddam, “…The device comprises a memory crossbar array comprising a plurality of row lines, a plurality of column lines and a plurality of junctions arranged between the plurality of row lines and the plurality of column lines. Each junction comprises a programmable resistive element and an access element for accessing the programmable resistive element…”)
Regarding claim 9, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein the first computing circuit is configured to generate the first output value, based on the currents supplied by the memory cells comprised in a read path among the first read paths (Khaddam teaches summation of currents produced by crossbar cells, [0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203. As an example, the readout circuit 12 reads out a current value b.sub.1 from the row line 201, which is the sum of three multiplications...”)
Regarding claim 14, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein the storage elements and the other storage elements are programmable resistive elements ([0026] of Khaddam, “…Resistive memory elements are based on a physical phenomenon occurring in a material that changes its resistance under action of a current or electric field. The change is usually non-volatile and reversible...”)
Regarding claim 15, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, further comprising a third computing circuit configured to generate another output value based on read currents supplied by one or more memory cells comprised in a read path among the first read paths and on the one or more first input values (crossbar systems include additional processing circuitry for neural network computation, [0033] of Khaddam, “…device 100 further comprises control circuitry 13 configured to control the signal generator 11 and the readout circuit 12…”).
Regarding claim 16, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 15, wherein the first and the third computing circuits are configured to generate the output values based on one or more cells in common in the plurality of first read paths, the common cells being duplicated in at least two parts in the first area (duplicating memory cells for redundancy is a conventional design practice in memory arrays).
Regarding claim 17, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein the one or more first input values are applied simultaneously to the first read paths (crossbar array apply input voltages simultaneously across rows, [0036] of Khaddam, “…matrix multiplication uses Ohm's law and Kirchhoff s law in a resistive memory crossbar array…”)
Regarding independent claim 18, the combination of Khaddam and Le Gallo teaches a method, comprising:
applying one or more first input values to a plurality of first read paths (e.g., read path through first memory area), each first read path comprising one among storage elements of a first plurality of storage elements of a first area of a non-volatile memory, the first plurality of storage elements being configured to store weight values associated with a first plurality of neurons of a neural network ([0021] of Khaddam, “…A fundamental computational primitive is a matrix-vector multiplication…”, [0036] of Khaddam, “…matrix multiplication uses Ohm's law and Kirchhoff s law in a resistive memory crossbar array…”, since the conductance values of the memory elements represent weights in the matrix, Khaddam teaches storage elements storing neural-network weight value, and applying input signals to rows of a resistive crossbar array storing neural-network weight);
adding first currents supplied by the first read paths to generate a first output current ([0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203….is the sum of three multiplications…”, Khaddam teaches adding read currents to generate an output current representing neural-network computation);
converting the first output current into a first programming current (Le Gallo teaches programming memory elements in an in-memory computing device using programming signals to adjust conductance values, [0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”); and
programming a first storage element of a second plurality of storage elements of a second area of the non-volatile memory using said first programming current (Le Gallo further teaches adjusting conductance values of memory elements to match target value, [0047] of Le Gallo, “…memory elements are adjusted …to match the summed conductance of the K memory elements of the cell with the target conductance value…”)
Regarding claim 19, the combination of Khaddam and Le Gallo teaches the method according to claim 18, further comprising (while claim 18 discuss read from first memory area, compute, program second memory area, claim 19 discuss read from second memory area, and program first memory area, claim 19 reverse the direction of the update, making it directional weight update between memory arrays): applying one or more second input values generated by reading the first one of the second plurality of storage elements to a plurality of second read paths (e.g., read path through second memory area), each second read path comprising one among the storage elements of the second plurality of storage elements (Khadam teaches applying input signals to rows of a resistive crossbar array storing neural -network weights);
adding second currents supplied by the second read paths to generate a second output current ([0047] of Khaddam, “…the readout circuit 12 reads out current values of the row lines 201, 202 and 203….is the sum of three multiplications…”, Khaddam teaches adding read currents to generate an output current representing neural-network computation); (Le Gallo teaches programming memory elements in an in-memory computing device using programming signals to adjust conductance values, [0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”); and
programming another storage element of the first area of the non-volatile memory by using said second programming current ([0014] of Le Gallo, “…the programming unit … is adapted to adjust the conductance value of said at least one of the K memory elements by applying voltage signals across the input lines or the output lines…”)
Regarding claim 20, the combination of Khaddam and Le Gallo teaches the method according to claim 18, where applying comprised applying the one or more first input values simultaneously to the first read paths (crossbar array apply input voltages simultaneously across rows, [0036] of Khaddam, “…matrix multiplication uses Ohm's law and Kirchhoff s law in a resistive memory crossbar array…”)
Claim 10-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khaddam-Aljameh PG PUB 20220293174 (hereinafter Khaddam), in view of Le Gallo-Bourdeau PG PUB 20240160348 (hereinafter Le Gallo), supported by Ambrogio, S., Narayanan, P., Tsai, H. et al. Equivalent-accuracy accelerated neural-network training using analogue memory. Nature 558, 60–67 (2018).
Regarding claim 10, the combination of Khaddam and Le Gallo, supported by Ambrogio, teaches the non-volatile memory according to claim 1, wherein the first computing circuit is further configured to apply compensation effects based on the currents supplied by the memory cells comprised in a read path among the first read paths (Analog crossbar readout circuits commonly include compensation circuitry to mitigate device variation, Khaddam teaches readout circuitry controlling crossbar operations, [0033] of Khaddam, “…device 100 further comprises control circuitry 13 configured to control the signal generator 11 and the readout circuit 12...”, Ambrogio teaches device variability and to use compensation circuits to correct analog errors. Compensation circuitry would have been an obvious implementation).
It is noted that compensation, thresholding, offset correction, and scaling are conventional signal-processing operations commonly used in analog signal-processing circuits and analog neural-networking accelerators to improve numerical stability, mitigate device variation, and ensure proper activation behavior. Such operations are routinely implemented in read-out and post-processing circuitry following analog matrix-vector multiplication in resistive memory crossbar systems. Therefore, implementing such operations in the computing circuitry of Khaddam would have been an obvious design choice for a person of ordinally skill in the art seeking to improve device performance.
Regarding claim 11, the combination of Khaddam and Le Gallo, supported by Ambrogio teaches the non-volatile memory according to claim 1, wherein the first computing circuit is further configured to apply threshold effects based on the currents supplied by the memory cells comprised in a read path among the first read paths (thresholding operations are standard neural-network post-processing steps, such signal conditioning is inherent in neural-network hardware, [0021] of Khaddam, Ambrogio teaches applying neural-network activation functions following analog matrix-vector multiplication, thresholding corresponding to the nonlinear activation function applied after matrix-vector multiplication).
Regarding claim 12, the combination of Khaddam and Le Gallo, supported by Ambrogio teaches the non-volatile memory according to claim 1, wherein the first computing circuit is further configured to apply offset effects based on the currents supplied by the memory cells comprised in a read path among the first read paths (Offset correction is a common calibration technique used in analog crossbar readout circuits to compensate systematic current errors, Ambrogio teaches correcting errors and device variations in analog neural-network crossbar system using signal correction and calibration techniques, offset correction is one form of such signal correction applied to neural-network outputs).
Regarding claim 13, the combination of Khaddam and Le Gallo teaches the non-volatile memory according to claim 1, wherein the first computing circuit is further configured to apply scaling effects based on the currents supplied by the memory cells comprised in a read path among the first read paths (Scaling of output is inherent in neural-network arithmetic and analog vector-matrix multiplication, Ambrogio teaches normalization and scaling of analog signals in neural-network accelerators).
Response To Arguments
Applicant's arguments filed 06/08/2026 have been fully considered but they are not persuasive.
Applicants argues: “neither Kaddam nor Le Gallo teaches converting an output current produced by summing read currents from a first plurality of storage elements into a programming current that used to program a storage element of a second plurality of storage elements. Kaddam's summed output current is not a programming current, and Le Gallo's voltage signals for programming are not programming currents and are not generated from summed read currents of other memory cells”.
Examiner respectfully disagrees.
Applicant argues that Le Gallo applied voltage signals rather than programming currents. However, the claims do not exclude programming currents generated by voltage-driven programming circuitry, not do the claims require any particular conversion mechanism.
Le Gallo teaches programming memory elements. The claims do not require any particular circuitry or algorithm for converting the first output current into the first programming current. Under BRI, the claimed “programming current” merely denotes a current used to program a storage element. Le Gallo teaches applying programming signals to adjust conductance values of memory elements. A person of ordinary skill in the art would have understood that such programming signals may be implemented as programming currents or voltage-controlled programming currents, depending on circuit implementation.
Applicant argues: “The second input values are what is being programmed into the first storage element in claim 1, and these second input values, as read from the first storage element, are used to generate the second read currents in claim 2. There is no teaching or suggestion in Kaddam or Le Gallo for using a programming current, generated by converting summed read currents, to program input values”.
Examiner does not agree with applicant’s interpretation of claim 2.
Claims 2 states: “second input values generated by reading the first storage element”, the claim does not state the programming current writes second input values into the first storage element.
Accordingly, the Examiner maintains the position previously set forth.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/XIAOCHUN L CHEN/Examiner, Art Unit 2824
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