DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zhang et al. (US 2015/0261698 A1), and further in view of Bacchus et al. (WO 2017/065802 A1).
Regarding claim 1, Zhang teaches an apparatus, comprising:
a first memory module that comprise one or more types of memory media, wherein the first memory module includes a first interface couplable to a host (Fig. 1, an interference 1011 coupled between a first memory module 101 and the host coupled to 103),
wherein the first interface is configured to transfer data or commands, or both, between the host and the first memory module via a first bus according to a first protocol (Fig. 1, the first interface 1011 configured to transfer data and commands between memory module 101 and host using a first bus 103),
wherein the first memory module includes a second interface couplable to a second memory module (Fig. 1, second interface 1012 is coupled to the second memory module 102); and
wherein the first interface and the second interface are configured to transfer data or commands, or both between the host and the second memory module via the first bus and a second bus according to a second protocol (first interface and second interface configured to transfer data and commands between the host and the second memory module 102 using a second bus 105).
Zhang did not explicitly teach whether the first interface is asynchronous or synchronous. Zhang does teach wherein the first protocol enables non-deterministic execution of commands.
Bacchus teaches a first interface uses a first protocol enables non-deterministic execution of commands (Fig. 1, Non-deterministic interface 108).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to non-deterministic protocol because it has a better power efficiency by preventing the system from wasting energy forcing idle wait states to match a fixed deterministic clock and latency. Also, non-deterministic protocol does not need a synchronization logic, which will reduce the hardware.
Regarding claim 2, Zhang teaches the apparatus of claim 1, wherein the first memory module comprises a DRAM array and a non-volatile memory array (memory module can have DRAM and Non-volatile memory, ¶0078).
Regarding claim 3, Zhang further teaches the apparatus of claim 1, wherein the first protocol is NVDIMM-P (¶0092).
Regarding claim 4, Zhang further teaches the apparatus of claim 1, wherein the second protocol is DDR5 (¶0092).
Regarding claim 5, Zhang further teaches the apparatus of claim 1, wherein the first memory module comprises a controller configured to control execution of commands according to the first protocol and the second protocol (Fig. 2, memory controller 206).
Regarding claim 6, Zhang further teaches the apparatus of claim 1, wherein the first memory module comprises a controller configured to transfer data or commands, or both, between the first interface and the second interface (Fig. 3A, Memory Management Unit 3011).
Regarding claim 7, Zhang further teaches the apparatus of claim 1, wherein the second interface is configured to transfer data or commands, or both, between the first memory module and the second memory module according to the second protocol in response to the first memory module receiving commands from the host according to the first protocol (Fig. 1, bus 103 receives data and command based on a first protocol and 105 receives data and command based on a second protocol).
Regarding claims 8-20, the claims have similar limitations as the claims above. Therefore, the claims are rejected under the same grounds of rejection.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Fukuzo (US 2006/0294295 A1), and further in view of Bacchus et al. (WO 2017/065802 A1).
Regarding claim 1, Fukuzo teaches an apparatus, comprising:
a first memory module that comprise one or more types of memory media, wherein the first memory module includes a first interface couplable to a host (Fig. 2, an interference 12 coupled between a first memory module 516 and the host 502),
wherein the first interface is configured to transfer data or commands, or both, between the host and the first memory module via a first bus according to a first protocol (Fig. 2, the first interface 12 configured to transfer data and commands between memory module 516 and host using a first bus 64),
wherein the first memory module includes a second interface couplable to a second memory module (Fig. 2, second interface 520 is coupled to the second memory module 514b); and
wherein the first interface and the second interface are configured to transfer data or commands, or both between the host and the second memory module via the first bus and a second bus according to a second protocol (first interface and second interface configured to transfer data and commands between the host and the second memory module 514b using a second bus).
Fukuzo does teach wherein the first protocol enables non-deterministic execution of commands.
Bacchus teaches a first interface uses a first protocol enables non-deterministic execution of commands (Fig. 1, Non-deterministic interface 108).
Thus, it would have been obvious to a person with the ordinary skill in the art before the effective filing date of the claimed invention to non-deterministic protocol because it has a better power efficiency by preventing the system from wasting energy forcing idle wait states to match a fixed deterministic clock and latency. Also, non-deterministic protocol does not need a synchronization logic, which will reduce the hardware.
Regarding claim 5, Fukuzo further teaches the apparatus of claim 1, wherein the first memory module comprises a controller configured to control execution of commands according to the first protocol and the second protocol (Fig. 4, SDRAM control logic 120).
Regarding claim 6, Fukuzo further teaches the apparatus of claim 1, wherein the first memory module comprises a controller configured to transfer data or commands, or both, between the first interface and the second interface (Fig. 4, SDRAM control logic 120).
Regarding claim 7, Fukuzo further teaches the apparatus of claim 1, wherein the second interface is configured to transfer data or commands, or both, between the first memory module and the second memory module according to the second protocol in response to the first memory module receiving commands from the host according to the first protocol (Fig. 3).
Regarding claims 8-20, the claims have similar limitations as the claims above. Therefore, the claims are rejected under the same grounds of rejection.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KHAMDAN N ALROBAIE whose telephone number is (571)270-7099. The examiner can normally be reached Monday to Thursday (8AM till 6PM).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Khamdan N. Alrobaie/Primary Examiner, Art Unit 2824
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