Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are presented for examination.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 5, 12 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 5 recites the limitation "the at least some insulating layers" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 12 recites the limitation "the at least some insulating layers" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim 19 recites the limitation "the at least some insulating layers" in line 1. There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5-8, 10 and 12-14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Naoki et al. (JP2015177013A1), hereafter referred to as Naoki.
As to claim 1, Naoki discloses a memory device (translation page 2), comprising:
a memory block (fig 2) including a stacked structure of alternating ones of a plurality of word lines (WL) and a plurality of insulating layers (40), the plurality of word lines including a plurality of memory cells (page 2);
a plurality of memory holes (MH/CL) extending through the word lines (WL) and through the insulating layers (40), the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines (page 6); and
the insulating layers having varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers (fig 12 and translation pages 9-10).
As to claim 3, Naoki discloses the memory device as set forth in claim 1 (paragraphs above),
wherein the insulating layers are dielectric layers (page 6).
As to claim 5, Naoki discloses the memory device as set forth in claim 1 (paragraphs above),
wherein the at least some insulating layers includes all of the insulating layers of the memory block (page 6).
As to claim 6, Naoki discloses the memory device as set forth in claim 1 (paragraphs above),
wherein the memory holes have frustoconical shapes (fig 4, MH).
As to claim 7, Naoki discloses the memory device as set forth in claim 1 (paragraphs above),
wherein the memory holes have upper portions and lower portions, and wherein each of the upper and lower portions has a frustoconical shape (fig 4, upper and lower portions of MH).
As to claim 8, Naoki discloses a method of making a memory device (figs 5-9), comprising the steps of:
building a memory block (fig 2) including a stacked structure of alternating ones of a plurality of word lines (WL) and a plurality of insulating layers (40), the plurality of word lines including a plurality of memory cells (page 2);
forming a plurality of memory holes (MH/CL) through the plurality of word lines (WL) and the insulating layers (40), the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines (page 6); and
wherein the insulating layers having varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers (fig 12 and translation pages 9-10).
As to claim 10, Naoki discloses the method as set forth in claim 8 (paragraphs above),
wherein the insulating layers are dielectric layers (page 6).
As to claim 12, Naoki discloses the method as set forth in claim 8 (paragraphs above),
wherein the at least some insulating layers includes all of the insulating layers of the memory block (page 6).
As to claim 13, Naoki discloses the method as set forth in claim 8 (paragraphs above),
wherein the memory holes have frustoconical shapes (fig 4, MH).
As to claim 14, Naoki discloses the method as set forth in claim 13 (paragraphs above),
wherein the memory holes have upper portions and lower portions, and wherein each of the upper and lower portions has a frustoconical shape (fig 4, upper and lower portions of MH).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 15, 17, 19 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Naoki in view of Yang et al. (US Pub. No. 2023/0041476 A1), hereafter referred to as Yang.
As to claim 15, Naoki discloses at least one non-volatile memory units (fig 2) including:
a memory block (fig 2) including a stacked structure of alternating ones of a plurality of word lines (WL) and a plurality of insulating layers (40), the plurality of word lines including a plurality of memory cells (page 2);
a plurality of memory holes (MH/CL) extending through the word lines (WL) and through the insulating layers (40), the memory holes having variable diameters such that the diameter of one of the memory holes at one of the word lines differs from the diameter of the same memory hole at another of the word lines (page 6); and
the insulating layers having varying thicknesses, the thicknesses of the insulating layers being determined as a function of the diameters of the memory holes in areas of the respective insulating layers (fig 12 and translation pages 9-10).
Naoki does not disclose a computing system, comprising:
a processor unit; and
a plurality of non-volatile memory units in electrical communication with the processor units.
Nonetheless, Yang discloses a computing system (fig 1; [0042]), comprising:
a processor unit (110); and
a plurality of non-volatile memory units in electrical communication with the processor units (104 with 110; [0042]-[0043]).
It would have been obvious to one of ordinary skill in the art before the effective filing of the claimed invention to include the memory device Naoki in a computing system as taught by Yang since this will better manage memory operations of the memory device.
As to claim 17, Naoki in view of Yang disclose the computing system as set forth in claim 15 (paragraphs above),
Naoki further discloses wherein the insulating layers are dielectric layers (page 6).
As to claim 19, Naoki in view of Yang disclose the computing system as set forth in claim 15 (paragraphs above),
Naoki further discloses wherein the at least some insulating layers includes all of the insulating layers of the memory block (page 6).
As to claim 20, Naoki in view of Yang disclose the computing system as set forth in claim 15 (paragraphs above),
Naoki further discloses wherein the memory holes have frustoconical shapes (fig 4, MH).
Allowable Subject Matter
Claims 2, 4, 9, 11, 16 and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record fails to teach or suggest wherein in a first location of the memory block, the memory holes have a relatively larger first diameter and in a second location of the memory block, the memory holes have a relatedly smaller second diameter, and wherein a first insulating layer in the first location of the memory block has a relatively lesser first thickness and wherein a second insulating layer in the second location of the memory block has a relatively greater second thickness, as recited in claims 2, 9 and 16; or wherein at least some of the insulating layers in the memory block have a thickness that is calculated according to the formula as recited in claims 4, 11 and 18.
Pertinent Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US Patent No. 10,748,627B2.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAUN M CAMPBELL whose telephone number is (571)270-3830. The examiner can normally be reached on MWFS: 7:30-6pm Thurs 1-2pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Purvis, Sue can be reached at (571)272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SHAUN M CAMPBELL/Primary Examiner, Art Unit 2893 9/18/2026
Prosecution Insights