DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-15 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-15 of U.S. Patent No.12,119,301. Although the claims at issue are not identical, they are not patentably distinct from each other because regarding claim 1, U.S. Patent No.12,119,301 discloses in claim 1, a semiconductor device, comprising: a substrate that includes a first side and a second side opposite to the first side; a first power line formed on the second side to which a first power potential is applied, a second power line formed on the second side to which a second power potential is applied, and a switch connected between the first power line and the second power line, a first grounding line formed on the first side, a third power line formed on the first side to which the second power potential is applied, a first region in which the first grounding line and the third power line are disposed, a second grounding line formed on the first side, a fourth power line formed on the first side to which the first power potential is applied, and a second region in which the second grounding line and the fourth power line are disposed, and in plan view, the switch is disposed between the first region and the second region. The first and second surface is equivalent to the first and second side.
Regarding claims 2-15, U.S. Patent No.12,119,301 discloses in claims 2-15, a semiconductor device as claimed in claim 1, wherein the second region includes a control circuit that is connected between the second grounding line and the fourth power line and is configured to control the switch; wherein the first grounding line and the second grounding line are electrically connected to each other; wherein the first power line includes a portion overlapping the second region in plan view, the second power line includes a portion overlapping the first region in plan view, and the first power line and second power line are connected to the switch between the first region and the second region; wherein the first power line and the second power line extend in a first direction in plan view, at least a portion of the first region and the second region are arranged along the first direction, a plurality of first power lines, including the first power line, to which the first power potential is applied, and a plurality of second power lines, including the second power line, to which the second power potential is applied, are arranged side by side in a second direction perpendicular to the first direction, and the switch is connected in common between the plurality of first power lines and the plurality of second power lines; wherein the first power line and the second power line extend in a first direction in plan view, the first region and the second region are arranged along a second direction perpendicular to the first direction in plan view, and a plurality of switches, including the switch, are connected between the first power line and the second power line; wherein the first grounding line and the third power line extend in the first direction; wherein a plurality of first power lines, including the first power line, to which the first power potential is applied, and a plurality of second power lines, including the second power line, to which the second power potential is applied, are arranged side by side along a second direction perpendicular to a first direction along which the first region and the second region are arranged side by side, the plurality of first power lines have respective first portions between the first region and the second region, the plurality of second power lines have respective second portions between the first region and the second region, the first portions and the second portions are alternately arranged in the second direction, and the switch is connected between a first portion of the first portions and a second portion of the second portions, the first portion and the second portion being arranged next to each other along the second direction; wherein a first portion of the first portions is shared by more than one of the plurality of first power lines, and a second portion of the second portions is shared by more than one of the plurality of second power lines; wherein the switch includes a semiconductor layer connected to the first power line and the second power line, a gate electrode, and a gate insulating film provided between the semiconductor layer and the gate electrode; wherein the gate insulating film is formed on a surface of the semiconductor layer that faces the substrate, and the gate electrode is formed on a surface of the gate insulating film that faces the substrate; wherein the gate insulating film is formed on a surface of the semiconductor layer opposite to a surface of the semiconductor layer that faces the substrate, and the gate electrode is formed on a surface of the gate insulating film opposite to a surface of the gate insulating film that faces the substrate; wherein a first switch group including a plurality of switches that include the switch, connected between the first power line and the second power line, and a second group of switches connected between the first power line and the second power line, are disposed, the first region being interposed between the first switch group and the second switch group in plan view, and the switches included in the first switch group and the switches included in the second switch group are alternately connected in parallel; wherein control terminals of the first switch group and control terminals of the second switch group are connected to each other via buffers outside the first region; further comprising capacitance elements connected to control terminals of the first switch group and to control terminals of the second switch group.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC-ANTHONY ARMAND whose telephone number is (571)272-5178. The examiner can normally be reached 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven B Gauthier can be reached at 571-270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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MARC - ANTHONY ARMAND
Primary Examiner
Art Unit 2813
/MARC-ANTHONY ARMAND/Primary Examiner, Art Unit 2813
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