FINAL REJECTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Applicant is advised that should claims 31-35 be found allowable, claims 38-42 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 31-34, 36-41, 44-48, 50, and 51 are rejected under 35 U.S.C. 103 as being unpatentable over Abellanas et al. (2014/0189696) in view of Allen-Ware et al. (2014/0149779).
Regarding claim 1:
Abellanas teaches:
One or more processors [par 43] comprising:
circuitry to:
obtain one or more error rates of one or more first cores of a plurality of cores [par 30, 32 – determines maximum error rates for each of a plurality of cores implementing one or more tasks, the rate expressed as percentages of a fixed global failure rate]
and a cumulative error rate threshold of the plurality of cores [par 32 – maximum failure rates are expressed as a percentage of a fixed global failure rate. A fixed global failure rate is a cumulative threshold for all the cores. The total of all failure rates cannot exceed the global rate]; and
cause one or more operating voltages of one or more second cores of the plurality of cores to be set resulting in a cumulative error rate of the plurality of cores to be below a cumulative error rate threshold based, at least in part, on the one or more error rates and a cumulative error rate of the plurality of cores [par 30, 33, 42 – the voltages of all cores are adjusted to maintain the cumulative total within the fixed global rate]
Abellanas does not explicitly teach the cores being integrated circuits. Abellanas does teach an SoC or a multi-die processor [par 52].
Allen-Ware teaches a multicore processor comprised of multiple integrated circuits [par 15 – “Processor 102 is a multicore processor where the processor cores are provided in chiplets “].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the chiplet core processor of Allen-Ware with the multicore processor of Abellanas.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because chiplets provide better performance than discreetly packaged devices and also provide greater production benefits [see, as extrinsic evidence, at least paragraph 3 of the cited Hornung reference (2022/0066869)].
Regarding claim 32:
The combination teaches:
The one or more processors of claim 31, wherein the one or more operating voltages of the one or more second integrated circuits are to be set based, at least in part, on the one or more error rates and the cumulative error rate of the plurality of integrated circuits remaining below a threshold error rate [Abellanas par 33 – expressed in some instances as percentages of a maximum global failure rate].
Regarding claim 33:
The combination teaches:
The one or more processors of claim 31, wherein the one or more operating voltages of the one or more second integrated circuits are to be set based, at least in part, on a table that correlates the one or more operating voltages of the one or more second integrated circuits with one or more error rates of the one or more second integrated circuits [Abellanas par 33 – “Then, a table with the core failure rates for each voltage may be accessed and the minimum that ensures that the desired failure rate is met may be selected.”].
Regarding claim 34:
The combination teaches:
The one or more processors of claim 31, wherein the one or more operating voltages of the one or more second integrated circuits are to be set based, at least in part, on a number and/or types of instructions to be performed by the one or more processors [Abellanas par 37 – “For example, the first task may be an operating system task and the second task may be a non-operating system task (e.g., a video decoding task, a graphics processing task, or another type of application task). As another example, the first task may be a main thread and the second task may be a sub-thread of the main thread (e.g., a child thread of a parent thread). In some embodiments, the first task (e.g., whose failure is highly undesirable) may be a real-time and/or time-critical task (e.g., a cell phone voice handling task) and the second task (e.g., whose failure is not as undesirable) may be a non-real time and/or non-time-critical task. In other embodiments, the first task (e.g., whose failure is highly undesirable) may be a bank database task or other similar commercial task that needs to have higher reliability and the second task (e.g., whose failure is not as undesirable) may be a task associated with other types of applications that are not as critical to have such high reliability”].
Regarding claim 36:
The combination teaches:
The one or more processors r of claim 31, wherein the one or more error rates of the one or more first integrated circuits is based, at least in part, on at least one of: operating voltage, operating temperature, and clock frequency of the one or more processors [Abellanas par 30 – “in order to implement the different maximum allowed failure rates (or minimum allowed reliability levels), different minimum allowed voltages may be used”].
Regarding claim 37:
The combination teaches:
The one or more processors of claim 31, wherein the circuitry is to obtain the one or more error rates of the one or more first integrated circuits of the plurality of integrated circuits by predicting the one or more error rates during a specified period of time [Abellanas par 6 – “The global failure rate may quantify the rate at which failures are predicted or expected to occur in the integrated circuit (e.g., the number of failures per unit time and/or the time between failures)”].
Regarding claims 38-41:
See the teachings of the combination regarding claims 31-34. Abellanas further teaches a system [par 24 – “Disclosed herein are embodiments of failure rate management methods, logic, processors, and systems”].
Regarding claims 44:
The combination teaches:
The system of claim 38, wherein the one or more error rates of the one or more first integrated circuits is based, at least in part, on a number of system part failures that are estimated to occur over a period of time [Abellanas par 6, 33 – “The global failure rate may quantify the rate at which failures are predicted or expected to occur in the integrated circuit (e.g., the number of failures per unit time and/or the time between failures),” ”in one illustrative example, an architectural vulnerability factor (AVF) of a hardware logic may be used as a derating factor. The hardware logic may be a whole core, a storage region, or other hardware with a relatively large impact on the overall failure rate”].
Regarding claims 45-48, 50 and 51:
See the teachings of the combination with respect to claims 31-34, 36 and 37. Abellenas teaches a method [par 24].
Claims 35, 42, and 49 are rejected under 35 U.S.C. 103 as being unpatentable over the Abellanas-Allen-Ware combination as applied to claims 31, 38, and 45 above, and further in view of Kegel et al. (2019/0235940).
Regarding claims 35, 42, and 39:
See the teachings of the combination above.
The combination does not explicitly teach wherein the one or more processors are to perform one or more artificial intelligence (Al) training and/or inferencing tasks. The combination does, however, teach performing a wide variety of tasks and managing the operating voltages in relation to the error processing those tasks.
Kegel teaches using power settings for managing an error rate of processors performing AI training and/or inferencing tasks [par 14, 15, 19].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the AI training/inferencing tasks of Kegel with the processors performing tasks of Abellanas-Allen-Ware.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because Abellanas-Allen-Ware teaches that processors can be used to perform myriad different tasks with varying error rate constraints or requirements without providing an exhaustive list of such tasks, creating an implicit need for listing of additional tasks the processors could perform. Kegel meets that need by providing disclosure regarding AI and/or inferencing tasks that manage error rates with power settings.
Claim 43 is rejected under 35 U.S.C. 103 as being unpatentable over Abellanas-Allen-Ware as applied to claim 38 above, and further in view of Zorn et al. (2011/0314210).
Regarding claim 43:
See the teachings of Abellanas-Allen-Ware above.
Abellanas-Allen-Ware does not explicitly teach wherein the one or more error rates of the one or more integrated circuits is based, at least in part, on empirical and/or simulated testing.
Zorn teaches one or more error rates of one or more integrated circuits is based, at least in part, on empirical and/or simulated testing [par 6, 21].
It would have been obvious to one of ordinary skill in the art prior to the effective filing date to combine the testing of Zorn with the error rate based adjustment of Abellanas-Allen-Ware.
One of ordinary skill in the art prior to the effective filing date would have been motivated to make the combination because Zorn teaches that such testing allows for power optimization, adjustments in reliability behavior, and unique identification of chips [par 4, 6].
Response to Arguments
Applicant's arguments filed 3/4/25 have been fully considered but they are not persuasive.
Regarding the objections to claims 38-42, applicant argues that the amendment renders the objections moot. The examiner respectfully disagrees. Claims 31-35 recites one or more processors comprising circuitry to perform actions. Claims 38-42 recite a system comprising one or more processors to perform identical actions as those of claims 31-35. There is no meaningful distinction between one or more processors comprising circuitry and a system comprising one or more processors.
Regarding the 35 USC 103 rejection of claims 31/34, 36-41, 44-48, 50, and 51, applicant argues that:
“For example, Abellanas describes that "a method 310 of failure rate based voltage control," and that "[i]n some embodiments, the method may be implemented in a processor or other integrated circuit." Abellanas at [0031]. Abellanas further describes "a processor 400 having failure rate based minimum voltage limiting logic 426," and that "the processor 400 may be a general-purpose processor (e.g., of the type used in desktop, laptop, server, and like computers)." Abellanas at [0043]-[0044]. Abellanas also describes that "[t]he processor includes a first core 402-1 through an Nth core 402-N," and that "[t]he first core is in a first voltage domain 422-1 and the Nth core is in an Nth voltage domain 422-N." Abellanas at [0045].
Furthermore, Abellanas describes that "[t]he processor may represent one or more monolithic integrated circuits or semiconductor die (e.g., a single die or a package incorporating two or more die)." Abellanas at [0052]. Abellanas also describes that the voltage regulation logic regulates "the voltage of the first voltage domain 422-1, the first core 402-1, and/or the first task 404-1," and similarly for the Nth core. Abellanas at [0045].
Accordingly, Abellanas appears to describe controlling voltages within a single processor die, not across a plurality of separate integrated circuits. Therefore, Abellanas does not disclose, teach, or suggest "caus[ing] one or more operating voltages of one or more second integrated circuits of the plurality of integrated circuits to be set resulting in a cumulative error rate of the plurality of integrated circuits to be below the cumulative error rate threshold based, at least in part, on the one or more error rates," as recited in claim 1.”
The examiner respectfully disagrees. Abbellanas discloses controlling voltages across a plurality of cores. Abellanas further teaches the processor can represent “one or more monolithic integrated circuits,” “two or more die,” etc. Further, the rejection did not rely solely on Abellanas to teach each and every limitation of the claims, rather, the rejection was based on a combination of references. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Applicant further argues that:
“Allen-Ware does not remedy Abellanas's deficiencies.
For example, Allen-Ware describes that "[p]rocessor 102 is a multicore processor where the processor cores are provided in chiplets 104," and that "[a]lthough three chiplets (e.g., chiplets 104A, 104B and 104C) are illustrated in FIG. 1, those of skill in the art having the benefit of the disclosure will appreciate that a processor 102 may have more or fewer chiplets 104." Allen-Ware at [0015]. Allen-Ware further describes that "chiplet 104 includes a processor core, memory (e.g., L2 and L3 cache) and supporting logic units for the processor core." Allen- Ware at [0016].
Accordingly, Allen-Ware appears to describe a multicore processor organized into chiplets within a single processor package. Therefore, Allen-Ware does not disclose, teach, or suggest a "obtain one or more error rates of one or more first integrated circuits of a plurality of integrated circuits and a cumulative error rate threshold of the plurality of integrated circuits," as recited in claim 1.”
Allen-Ware was not relied upon to teach obtaining "one or more error rates of one or more first integrated circuits of a plurality of integrated circuits and a cumulative error rate threshold of the plurality of integrated circuits.” Again, the rejection is based on a combination of references. One cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
The rejection is maintained.
The remaining arguments rely on the same arguments provided in regard to independent claim 31.
The rejections are maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARC M DUNCAN whose telephone number is (571)272-3646. The examiner can normally be reached M-F: 730am-9am, 10am-4:30pm.
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/MARC DUNCAN/Primary Examiner, Art Unit 2113
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