DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 9, 11, 13-15, 17, 19 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pang et al. (Pang) (CN 117457739 A).
In regards to claim 1, Pang (Figs. 1, 10 and associated text) discloses a power semiconductor device (Fig. 1) comprising: a substrate of a first conductivity type (item 1011, N-type); a drift layer of a first conductivity type (item 1012, N-type) on the substrate (item 1011); a well region of a second conductivity type (item 103, P-type) on the drift layer (item 1011); a source region of the first conductivity type (item 105, N-type) on the well region (item 103); a gate electrode (item 110) disposed in a gate trench (shown but not labeled) extending into the source region (item 105) and the well region (item 103); a first gate insulating layer (items 107, 1071), a second gate insulating layer (item 108, 1081), and a third gate insulating layer (item 109, 1091) disposed between the well region (item 103) and the gate electrode (item 110); a dielectric layer (item 111) on the gate electrode (item 110); and a drain electrode (item 113) on a lower surface of the substrate (item 1011), wherein the first gate insulating layer (items 107, 1071) has a first dielectric constant (dielectric constant of silicon dioxide), wherein the second gate insulating layer (items 108, 1081) has a second dielectric constant (dielectric constant of hafnium oxide)greater than the first dielectric constant (dielectric constant of silicon dioxide), and wherein the third gate insulating layer (items 109, 1091) has a first thickness on a bottom surface of the gate trench (shown but not labeled) and a second thickness, less than the first thickness, on a sidewall of the gate trench (shown but not labeled).
In regards to claim 2, Pang (Figs. 1, 10 and associated text) discloses wherein the first gate insulating layer items 107, 1071) contacts the well region and the source region within the gate trench (shown but not labeled), wherein the second gate insulating layer (items 108, 1081)is on the first gate insulating layer (items 107, 1071), and wherein the third gate insulating layer (items 109, 1091) is disposed on the second gate insulating layer (items 108, 1091) and contacts a side surface and a bottom surface of the gate electrode (item 110). Examiner notes the Applicant has not given a special definition the term “contact”, therefore certain claimed features may be in “indirect” or “direct” contact with one another.
In regards to claim 3, Pang (Figs. 1, 10 and associated text) discloses wherein the first gate insulating layer (items 107, 1071) has a third thickness (thickness of items 107, 1071) less than the first thickness (thickness of items 109, 1091) on the bottom surface of the gate trench (shown but not labeled).
In regards to claim 9, Pang (Figs. 1, 10 and associated text) discloses wherein the third gate insulating layer (items 109, 1091) has a third dielectric constant (dielectric constant of silicon dioxide) less than the second dielectric constant (dielectric constant of hafnium oxide).
In regards to claim 11, Pang (Figs. 1, 10 and associated text) discloses wherein the third gate insulating layer (items 109, 1091) includes the same insulating material (silicon dioxide) as the first gate insulating layer (items 107, 1071).
In regards to claim 13, Pang (Figs. 1, 10 and associated text) discloses wherein the substrate (item 1011), the drift layer (item 1012), and the well region (item 103) comprise silicon carbide (SiC).
In regards to claim 14, Pang (Figs. 1, 10 and associated text) discloses a power semiconductor device (Fig. 1) comprising: a substrate of a first conductivity type (item 1011, N-type); a drift layer of a first conductivity type (item 1012, N-type) on the substrate (item 1011); a well region of a second conductivity type (item 103, P-type) on the drift layer (item 1011); a source region of the first conductivity type (item 105, N-type) on the well region (item 103); a gate electrode (item 110) disposed in a gate trench (shown but not labeled) extending into the source region (item 105) and the well region (item 103); gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) including a first gate insulating layer (items 107, 1071), a second gate insulating layer (item 108, 1081), and a third gate insulating layer (item 109, 1091) disposed between the well region (item 103) and the gate electrode (item 110); a dielectric layer (item 111) on the gate electrode (item 110); and a drain electrode (item 113) on a lower surface of the substrate (item 1011), wherein the second gate insulating layer (item 108, 1081) includes an insulating material (hafnium oxide) different from insulating materials (silicon dioxide) of the first gate insulating layer (item 107, 1071) and the third gate insulating layer (item 109, 1091), and wherein the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) have a first thickness on a bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface) of the gate trench and a second thickness bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the sidewall surface), less than the first thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface), on a sidewall of the gate trench (shown but not labeled).
In regards to claim 15, Pang (Figs. 1, 10 and associated text) discloses wherein a thickness of the third gate insulating layer (item 109, 1091) on the bottom surface of the gate trench (shown but not labeled) is thicker than a thickness of the first gate insulating layer (item 107, 1071) on the bottom surface of the gate trench (shown but not labeled) and a thickness of the second gate insulating layer (item 108, 1081)on the bottom surface of the gate trench (shown but not labeled).
In regards to claim 17, Pang (Figs. 1, 10 and associated text) discloses wherein the second gate insulating layer (items 108, 1081) has a dielectric constant (dielectric constant of hafnium oxide) greater than a dielectric constant (dielectric constant of silicon dioxide) of the first gate insulating layer (items 107, 1071) and a dielectric constant (dielectric constant of silicon dioxide) of the third gate insulating layer (items 109, 1091).
In regards to claim 19, Pang (Figs. 1, 10 and associated text) discloses a power semiconductor device (Fig. 1) comprising: a substrate of a first conductivity type (item 1011, N-type); a drift layer of a first conductivity type (item 1012, N-type) on the substrate (item 1011); a well region of a second conductivity type (item 103, P-type) on the drift layer (item 1011); a source region of the first conductivity type (item 105, N-type) on the well region (item 103); a gate electrode (item 110) disposed in a gate trench (shown but not labeled) extending into the source region (item 105) and the well region (item 103); gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) disposed between the well region (item 103) and the gate electrode (item 110), the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) having a first thickness on a bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface) of the gate trench (shown but not labeled) and a second thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the sidewall surface), less than the first thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface), on a sidewall of the gate trench (shown but not labeled); a dielectric layer (item 111) on the gate electrode (item 110); and a drain electrode (item 113) on a lower surface of the substrate (items 1011), wherein the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) includes a first gate insulating layer (item 107, 1071) on the sidewall of the gate trench; a second gate insulating layer (item 108, 1081) on the first gate insulating layer (item 107, 1071); and a third gate insulating layer (item 109, 1091) disposed on the second gate insulating layer (item 108, 1081) and in contact with the gate electrode (item 110), and wherein the third gate insulating layer (item 109, 1091) has a third thickness on the bottom surface (thickness of item 109, 1091 on the bottom surface) of the gate trench and a fourth thickness (thickness of item 109, 1091 on the sidewall surface) less than the third thickness (thickness of item 109, 1091 on the bottom surface) on the sidewall of the gate trench (shown but not labeled).
In regards to claim 20, Pang (Figs. 1, 10 and associated text) discloses wherein the gate electrode (item 110) has a first width in a horizontal direction and a second width narrower than the first width in a vertical direction.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4, 9-12 and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (Lu) (CN 114267741 A) in view of Li et al. (Li) (CN 116031293 A).
In regards to claim 1, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); a first gate insulating layer (item 208), a second gate insulating layer (item 209), and a third gate insulating layer (item 210) disposed between the well region (item 203) and the gate electrode (item 211); a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the first gate insulating layer (item 208) has a first dielectric constant (dielectric constant of silicon dioxide), wherein the second gate insulating layer (item 209) has a second dielectric constant (dielectric constant of silicon nitride or TixZrySizO) greater than the first dielectric constant (dielectric constant of silicon dioxide), but does not disclose wherein the third gate insulating layer (item 210) has a first thickness on a bottom surface (thickness of 210 at the bottom surface) of the gate trench (item 207) and a second thickness (thickness of 210 at the sidewall surface), less than the first thickness (thickness of 210 at the bottom surface), on a sidewall of the gate trench (item 207).
Li (Fig. 1 and associated text) discloses wherein the third gate insulating layer (item 10) has a first thickness on a bottom surface (thickness of item 10 on the bottom surface) of the gate trench (shown but not labeled) and a second thickness (thickness of item 10 on the sidewall surface), less than the first thickness (thickness of item 10 on the bottom surface), on a sidewall of the gate trench (shown but not labeled).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 2, Lu (Fig. 2l and associated text) discloses wherein the first gate insulating layer (item 208) contacts the well region (item 203) and the source region (item 205) within the gate trench (item 207), wherein the second gate insulating layer (item 209) is on the first gate insulating layer (item 208), and wherein the third gate insulating layer (item 210) is disposed on the second gate insulating layer (item 29) and contacts a side surface and a bottom surface of the gate electrode (item 211).
In regards to claim 3, Lu (Fig. 2l and associated text) alone, or as modified by Li (Fig. 1 and associated text) discloses wherein the first gate insulating layer (item 208, Lu, item 8, Li) has a third thickness(thickness of 208 at the bottom surface, Lu, thickness of item 8 at the bottom surface) less than the first thickness (thickness of 210 at the bottom surface, Lu, thickness of item 10 at the bottom surface) on the bottom surface of the gate trench (item 207, Lu, shown but not labeled, Li).
In regards to claim 4, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein a lower surface of the third gate insulating layer (item 210, Lu, item 10, Li) corresponds to a surface profile of the gate trench (item 207, Lu, shown but not labeled, Li), and wherein an upper surface of the third gate insulating layer (item 210, Lu, item 10, Li) includes a side surface facing the sidewall of the gate trench (item 210, Lu, item 10, Li) and a flat surface (flat surface of item 10, Li) extending from the side surface within the gate trench (item 210, Lu, item 10, Li).
In regards to claim 9, Lu (Fig. 2l and associated text) as modified by Li discloses wherein the third gate insulating layer (item 210) has a third dielectric constant (dielectric constant of silicon dioxide) less than the second dielectric constant (dielectric constant of silicon nitride or TixZrySizO).
In regards to claim 10, Lu as modified by Li does not specifically disclose wherein the third gate insulating layer has a third dielectric constant less than the first dielectric constant.
It would have been obvious to modify the invention to include a third gate insulating layer having a third dielectric constant less than the first dielectric constant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 11, Lu (Fig. 2l and associated text) as modified by Li discloses wherein the third gate insulating layer (item 210) includes the same insulating material (silicon dioxide) as the first gate insulating layer (item 208).
In regards to claim 12, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein the first gate insulating layer (item 208, Lu, item 8, Li), the second gate insulating layer (item 209, Lu, item 9, Li), and the third gate insulating layer (item 210, Lu, item 10, Li) extend onto the source region (item 205, Lu), and wherein an upper surface of the third gate insulating layer (item 210, Lu, item 10, Li) on the source region (item 205, Lu) is disposed at a level higher than a level of an upper surface of the gate electrode (item 211, Lu).
In regards to claim 14, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); gate insulating layers (items 208 plus 209 plus 210) including a first gate insulating layer (item 208), a second gate insulating layer (item 209), and a third gate insulating layer (item 210) sequentially disposed between the well region (item 203) and the gate electrode (item 211); a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the second gate insulating layer (item 209) includes an insulating material (silicon nitride or TixZrySizO) different from insulating materials (silicon dioxide) of the first gate insulating layer (item 208) and the third gate insulating layer (item 208), but does not specifically disclose wherein the gate insulating layers have a first thickness on a bottom surface of the gate trench and a second thickness, less than the first thickness, on a sidewall of the gate trench.
Li (Fig. 1 and associated text) discloses wherein the gate insulating layers (items 8 plus 9 plus 10) have a first thickness on a bottom surface (thickness of items 8 plus 9 plus 10 on the bottom surface) of the gate trench and a second thickness (thickness of items 8 plus 9 plus 10 on the sidewall surface), less than the first thickness (thickness of items 8 plus 9 plus 10 on the bottom surface), on a sidewall of the gate trench (shown but not labeled).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 15, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein a thickness of the third gate insulating layer (item 210, Lu, item 10, Li) on the bottom surface of the gate trench is thicker than a thickness of the first gate insulating layer (item 208, Lu, item 8, Li) on the bottom surface of the gate trench and a thickness of the second gate insulating layer (item 209, Lu, item 9, Li) on the bottom surface of the gate trench.
In regards to claim 16, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein the gate insulating layers (item 208 plus 209 plus 210, Lu, items 8 plus 9 plus 10, Li) extend onto the source region (item 205, Lu), and wherein a thickness of the third gate insulating layer (item 210, Lu, item 10, Li) on the source region (item 205), Lu) is less than a thickness of the gate insulating layer (item 210, Lu, item 10, Li) on the bottom surface of the gate trench and is greater than a thickness of the third gate insulating layer (item 210, Lu, item 10, Li) on the sidewall of the gate trench.
In regards to claim 17, Lu (Fig. 2l and associated text) discloses wherein the second gate insulating layer (item 209) has a dielectric constant (dielectric constant of silicon nitride or TixZrySizO) greater than a dielectric constant (dielectric constant of silicon dioxide) of the first gate insulating layer (item 209) and a dielectric constant (dielectric constant of silicon dioxide) of the third gate insulating layer (item 210).
In regards to claim 18, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein a thickness of the first gate insulating layer (item 208, Lu, item 8, Li) on the bottom surface of the gate trench is less than a thickness of the first gate insulating layer (item 208, Lu, item 8, Li) on the sidewall of the gate trench.
It would have been obvious to modify the invention to include a thickness of the first gate insulating layer on the bottom surface of the gate trench being less than a thickness of the first gate insulating layer on the sidewall of the gate trench, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 19, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); gate insulating layers (items 208 plus 209 plus 210) disposed between the well region (item 203) and the gate electrode (item 2211), a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the gate insulating layers (items 208 plus 209 plus 210) includes a first gate insulating layer (item 208) on the sidewall of the gate trench; a second gate insulating layer (item 209) on the first gate insulating layer (item 208); and a third gate insulating layer (item 210) disposed on the second gate insulating layer (item 209) and in contact with the gate electrode (item 211), but does not specifically disclose the gate insulating layers (items 208 plus 209 plus 210) having a first thickness on a bottom surface of the gate trench and a second thickness, less than the first thickness, on a sidewall of the gate trench; wherein the third gate insulating layer (item 210) has a third thickness on the bottom surface of the gate trench and a fourth thickness less than the third thickness on the sidewall of the gate trench.
Li (Fig. 1 and associated text) discloses the gate insulating layers (items 8 plus 9 plus 10) having a first thickness on a bottom surface (thickness of items 8 plus 9 plus 10 on the bottom surface) of the gate trench and a second thickness (thickness of items 8 plus 9 plus 10 on the sidewall surface), less than the first thickness (thickness of items 8 plus 9 plus 10 on the bottom surface), on a sidewall of the gate trench; wherein the third gate insulating layer (item 10) has a third thickness on the bottom surface (thickness of item 10 on the bottom surface) of the gate trench and a fourth thickness (thickness of item 10 on the sidewall surface) less than the third thickness (thickness of item 10 on the bottom surface) on the sidewall of the gate trench.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 20, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) discloses wherein the gate electrode (item 211, Lu, item 11, Li) has a first width in a horizontal direction (width of item 11 in the horizontal direction, Li) and a second width narrower than the first width in a vertical direction (width/height of item 11 in the vertical direction, Li).
It would have been obvious to modify the invention to include a gate electrode having a first width in a horizontal direction and a second width narrower than the first width in a vertical direction, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Examiner notes that Applicant has not given any criticality to any shapes and/or dimensions that yield an advantage/unexpected result.
Claim(s) 5-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (Lu) (CN 114267741 A) in view of Li et al. (Li) (CN 116031293 A) as applied to claims 1-4 above and further in view of Yu et al. (YU) (KR 102373622 B1).
In regards to claim 5, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) does not specifically disclose wherein the gate electrode (item 211, Lu, item 11, Li) does not overlap the second gate insulating layer in a vertical direction.
Yu (Fig. 5 and associated text) discloses a gate insulating layer (item 235) can have just a vertically linear shape/portion or l-shape.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of o Yu, since such a modification would have involved a mere change in the shape of a component. A change in shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
Examiner takes the position that Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) and Yu (Fig. 5 and associated text) discloses wherein the gate electrode (item 211, Lu, item 11, Li) does not overlap the second gate insulating layer (item 209, Lu, item 9, Li) in a vertical direction.
In regards to claim 6, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) and Yu (Fig. 5 and associated text) discloses wherein the third gate insulating layer (item 210, Lu, item 10, Li) is in contact with the first gate insulating layer (item 208, Lu, item 8, Li) on the bottom surface of the gate trench (item 207, Lu, shown but not labeled, Li).
In regards to claim 7, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) and Yu (Fig. 5 and associated text) discloses wherein the gate electrode (item 211, Lu, item 11, Li) does not overlap the first gate insulating layer (item 208, Lu, item 8, Li) and the second gate insulating layer (item 209, Lu, item 9, Li) in a vertical direction.
In regards to claim 8, Lu (Fig. 2l and associated text) as modified by Li (Fig. 1 and associated text) and Yu (Fig. 5 and associated text) discloses wherein the third gate insulating layer (item 210, Lu, item 10, Li) contacts the drift layer (item 202, Lu) on the bottom surface of the gate trench (item 207, Lu, shown but not labeled, Li).
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (Lu) (CN 114267741 A) in view of Li et al. (Li) (CN 116031293 A) as applied to claims 1-4, 9-12 above and further in view of Kim et al. (Kim) (US 2025/0120133 A1).
In regards to claim 13, Lu as modified by Li does not specifically disclose wherein the substrate, the drift layer, and the well region comprise silicon carbide (SiC).
Kim (paragraphs 101-105, Fig. 2C and associated text) discloses wherein the substrate (item 110), the drift layer (item 120), and the well region (item 130) comprise silicon carbide (SiC).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Li for the purpose silicon carbide power MOSFET, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
Claim(s) 1-3, 9-11, 13-15 and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lu et al. (Lu) (CN 114267741 A) in view of Pang et al. (Pang) (CN 117457739 A).
In regards to claim 1, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); a first gate insulating layer (item 208), a second gate insulating layer (item 209), and a third gate insulating layer (item 210) disposed between the well region (item 203) and the gate electrode (item 211); a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the first gate insulating layer (item 208) has a first dielectric constant (dielectric constant of silicon dioxide), wherein the second gate insulating layer (item 209) has a second dielectric constant (dielectric constant of silicon nitride or TixZrySizO) greater than the first dielectric constant (dielectric constant of silicon dioxide), but does not disclose wherein the third gate insulating layer (item 210) has a first thickness on a bottom surface (thickness of 210 at the bottom surface) of the gate trench (item 207) and a second thickness (thickness of 210 at the sidewall surface), less than the first thickness (thickness of 210 at the bottom surface), on a sidewall of the gate trench (item 207).
Pang (Figs. 1, 10 and associated text) discloses wherein the third gate insulating layer (items 109, 1091) has a first thickness on a bottom surface of the gate trench (shown but not labeled) and a second thickness, less than the first thickness, on a sidewall of the gate trench (shown but not labeled).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Pang for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 2, Lu (Fig. 2l and associated text) discloses wherein the first gate insulating layer (item 208) contacts the well region (item 203) and the source region (item 205) within the gate trench (item 207), wherein the second gate insulating layer (item 209) is on the first gate insulating layer (item 208), and wherein the third gate insulating layer (item 210) is disposed on the second gate insulating layer (item 29) and contacts a side surface and a bottom surface of the gate electrode (item 211).
In regards to claim 3, Lu (Fig. 2l and associated text) alone, or as modified by Pang (Figs. 1, 10 and associated text) discloses wherein the first gate insulating layer (item 208, Lu, item 107/1071, Pang) has a third thickness (thickness of 208 at the bottom surface, Lu, thickness of item 107/1071 at the bottom surface, Pang) less than the first thickness (thickness of 210 at the bottom surface, Lu, thickness of item 109/1091 at the bottom surface, Pang) on the bottom surface of the gate trench (item 207, Lu, shown but not labeled, Pang).
In regards to claim 9, Lu (Fig. 2l and associated text) and Pang (See anticipatory rejection of Pang above) both disclose wherein the third gate insulating layer (item 210) has a third dielectric constant (dielectric constant of silicon dioxide) less than the second dielectric constant (dielectric constant of silicon nitride or TixZrySizO).
In regards to claim 10, Lu as modified by Pang does not specifically disclose wherein the third gate insulating layer has a third dielectric constant less than the first dielectric constant.
It would have been obvious to modify the invention to include a third gate insulating layer having a third dielectric constant less than the first dielectric constant, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 11, Lu (Fig. 2l and associated text) and Pang (See anticipatory rejection of Pang above) both disclose wherein the third gate insulating layer (item 210) includes the same insulating material (silicon dioxide) as the first gate insulating layer (item 208).
In regards to claim 13, Lu as modified by Pang (Figs. 1, 10 and associated text) discloses wherein the substrate (item 1011), the drift layer (item 1012), and the well region (item 103) comprise silicon carbide (SiC).
In regards to claim 14, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); gate insulating layers (items 208 plus 209 plus 210) including a first gate insulating layer (item 208), a second gate insulating layer (item 209), and a third gate insulating layer (item 210) sequentially disposed between the well region (item 203) and the gate electrode (item 211); a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the second gate insulating layer (item 209) includes an insulating material (silicon nitride or TixZrySizO) different from insulating materials (silicon dioxide) of the first gate insulating layer (item 208) and the third gate insulating layer (item 208), but does not specifically disclose wherein the gate insulating layers have a first thickness on a bottom surface of the gate trench and a second thickness, less than the first thickness, on a sidewall of the gate trench.
Pang (Figs. 1, 10 and associated text) discloses wherein the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) have a first thickness on a bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface) of the gate trench and a second thickness bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the sidewall surface), less than the first thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface), on a sidewall of the gate trench (shown but not labeled).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Pang for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 15, Lu (Fig. 2l and associated text) and Pang (See anticipatory rejection of Pang above) both disclose wherein a thickness of the third gate insulating layer (item 210, Lu, item 10, Li) on the bottom surface of the gate trench is thicker than a thickness of the first gate insulating layer (item 208, Lu, item 8, Li) on the bottom surface of the gate trench and a thickness of the second gate insulating layer (item 209, Lu, item 9, Li) on the bottom surface of the gate trench.
In regards to claim 17, Lu (Fig. 2l and associated text) and Pang (See anticipatory rejection of Pang above) both disclose wherein the second gate insulating layer (item 209) has a dielectric constant (dielectric constant of silicon nitride or TixZrySizO) greater than a dielectric constant (dielectric constant of silicon dioxide) of the first gate insulating layer (item 209) and a dielectric constant (dielectric constant of silicon dioxide) of the third gate insulating layer (item 210).
In regards to claim 18, Lu (Fig. 2l and associated text) as modified by Pang (Figs. 1, 10 and associated text) discloses wherein a thickness of the first gate insulating layer (item 208, Lu, item 107/1071, Pang) on the bottom surface of the gate trench is less than a thickness of the first gate insulating layer (item 208, Lu, item 107/1071, Pang) on the sidewall of the gate trench.
It would have been obvious to modify the invention to include a thickness of the first gate insulating layer on the bottom surface of the gate trench being less than a thickness of the first gate insulating layer on the sidewall of the gate trench, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 19, Lu (Fig. 2l and associated text) discloses a power semiconductor device (Fig. 2l) comprising: a substrate of a first conductivity type (item 201, N-type); a drift layer of a first conductivity type (item 202, N-type) on the substrate (item 201); a well region of a second conductivity type (item 203, P-type) on the drift layer (item 202); a source region of the first conductivity type (item 205, N-type) on the well region (item 203); a gate electrode (item 211) disposed in a gate trench (item 207) extending into the source region (item 205) and the well region (item 203); gate insulating layers (items 208 plus 209 plus 210) disposed between the well region (item 203) and the gate electrode (item 2211), a dielectric layer (item 212) on the gate electrode (item 211); and a drain electrode (item 215) on a lower surface of the substrate (item 201), wherein the gate insulating layers (items 208 plus 209 plus 210) includes a first gate insulating layer (item 208) on the sidewall of the gate trench; a second gate insulating layer (item 209) on the first gate insulating layer (item 208); and a third gate insulating layer (item 210) disposed on the second gate insulating layer (item 209) and in contact with the gate electrode (item 211), but does not specifically disclose the gate insulating layers (items 208 plus 209 plus 210) having a first thickness on a bottom surface of the gate trench and a second thickness, less than the first thickness, on a sidewall of the gate trench; wherein the third gate insulating layer (item 210) has a third thickness on the bottom surface of the gate trench and a fourth thickness less than the third thickness on the sidewall of the gate trench.
Pang (Figs. 1, 10 and associated text) discloses a power semiconductor device (Fig. 1) comprising: a substrate of a first conductivity type (item 1011, N-type); a drift layer of a first conductivity type (item 1012, N-type) on the substrate (item 1011); a well region of a second conductivity type (item 103, P-type) on the drift layer (item 1011); a source region of the first conductivity type (item 105, N-type) on the well region (item 103); a gate electrode (item 110) disposed in a gate trench (shown but not labeled) extending into the source region (item 105) and the well region (item 103); gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) disposed between the well region (item 103) and the gate electrode (item 110), the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) having a first thickness on a bottom surface (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface) of the gate trench (shown but not labeled) and a second thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the sidewall surface), less than the first thickness (thickness of items 107/1071 plus 108/1081 plus 109/1091 on the bottom surface), on a sidewall of the gate trench (shown but not labeled); a dielectric layer (item 111) on the gate electrode (item 110); and a drain electrode (item 113) on a lower surface of the substrate (items 1011), wherein the gate insulating layers (items 107/1071 plus 108/1081 plus 109/1091) includes a first gate insulating layer (item 107, 1071) on the sidewall of the gate trench; a second gate insulating layer (item 108, 1081) on the first gate insulating layer (item 107, 1071); and a third gate insulating layer (item 109, 1091) disposed on the second gate insulating layer (item 108, 1081) and in contact with the gate electrode (item 110), and wherein the third gate insulating layer (item 109, 1091) has a third thickness on the bottom surface (thickness of item 109, 1091 on the bottom surface) of the gate trench and a fourth thickness (thickness of item 109, 1091 on the sidewall surface) less than the third thickness (thickness of item 109, 1091 on the bottom surface) on the sidewall of the gate trench (shown but not labeled).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Pang for the purpose of thermal stability and interface quality, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of
ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)).
In regards to claim 20, Lu (Fig. 2l and associated text) and Pang (Figs. 1, 10 and associated text) both disclose wherein the gate electrode (item 211, Lu, item 110, Pang) has a first width in a horizontal direction (width of item 11 in the horizontal direction, Li, width of item 110 in the horizontal direction, Pang) and a second width narrower than the first width in a vertical direction (width/height of item 11 in the vertical direction, Li, width/height of item 110 in the horizontal direction, Pang).
It would have been obvious to modify the invention to include a gate electrode having a first width in a horizontal direction and a second width narrower than the first width in a vertical direction, since such a modification would have involved a mere change in the size/shape of a component. A change in size/shape is generally recognized as being within the level of ordinary skill in the art (In re Rose, 105 USPQ 237 (CCPA 1955)). Examiner notes that Applicant has not given any criticality to any shapes and/or dimensions that yield an advantage/unexpected result.
Conclusion
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TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 September 5, 2026
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