DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
1. Amendment filed on 06/15/2026 has been entered. Claims 1 and 3 are amended and claims 7-8 are canceled.
Response to Arguments
2. Applicant contends, “in Xu, a gate of T4 receives a clock signal and a gate of T5 receives a Gout2 signal.” Examiner respectfully disagrees. Paragraph [0226] of Xu discloses that Gout2 or (K5) can be any of the plurality of clock signals. It is obvious that the plurality of clock signals includes CLK1 as illustrated in fig. 17
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
3. Claim(s) 1, 3, 9, and 12 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Xu et al (US 2024/0379063).
As to claim 1, Xu teaches a driving circuit comprising a plurality of stages that output a plurality of gate signals to a plurality of pixels, wherein each of the plurality of stages (plurality of stages, [0672]) comprises:
a first transistor (T2, fig. 17) connected between a first terminal (input, fig. 17) and a first node and configured to control a voltage level of the first node (N3, fig. 17), wherein the first terminal receives a first signal ([0265] the functional input terminal includes the first voltage signal terminal); a second transistor (T4, fig. 17) connected between a second terminal (VGL) and a second node and configured to control a voltage level of the second node (N2, fig. 17), wherein the second terminal receives a second signal (VGL, fig. 17); a third transistor (T5, fig. 17) connected between a third terminal (S3, fig. 17) and the second node and configured to control the voltage level of the second node (N2, fig. 17), wherein the third terminal receives a third signal (CLK1, fig. 17); and an output circuit (an output circuit including T16 and T17, fig. 17) configured to output a corresponding gate signal (Gout1, fig. 17), among the plurality of gate signals, of one of a high-level voltage and a low-level voltage (see Gout1 in figure 33) according to the voltage level of the first node (N3, fig. 17) and the voltage level of the second node (N2, fig. 17), wherein channel type of the first transistor (T2 is a p-type, fig. 17) and a channel type of the third transistor are different from each other (T5 is an n-type transistor, fig. 17),
wherein a gate of the second transistor (T4, fig. 17) is connected to a gate of the third transistor (T5, fig. 17, [0226] The fifth control signal terminal K5 may be one of the plurality of clock signal terminals. Examiner’s Note: the plurality of clock signal terminals may include CLK1 as illustrated in fig. 17), and wherein the gate of the second transistor and the gate of the third transistor receive a same signal (CLK1, fig. 17).
As to claim 3, Xu teaches a driving circuit comprising a plurality of stages that output a plurality of gate signals to a plurality of pixels, wherein each of the plurality of stages (plurality of stages, [0672]) comprises:
a first transistor (T2, fig. 17) connected between a first terminal (input, fig. 17) and a first node and configured to control a voltage level of the first node (N3, fig. 17), wherein the first terminal receives a first signal ([0265] the functional input terminal includes the first voltage signal terminal); a second transistor (T4, fig. 17) connected between a second terminal (VGL) and a second node and configured to control a voltage level of the second node (N2, fig. 17), wherein the second terminal receives a second signal (VGL, fig. 17); a third transistor (T5, fig. 17) connected between a third terminal (S3, fig. 17) and the second node with a gate of the third transistor connected to a first clock terminal receiving a first clock signal (T5, fig. 17, [0226] The fifth control signal terminal K5 may be one of the plurality of clock signal terminals. Examiner’s Note: the plurality of clock signal terminals may include CLK1 as illustrated in fig. 17), the third transistor configured to control the voltage level of the second node (N2, fig. 17), wherein the third terminal receives a third signal (CLK1, fig. 17); and an output circuit (an output circuit including T16 and T17, fig. 17) configured to output a corresponding gate signal (Gout1, fig. 17), among the plurality of gate signals, of one of a high-level voltage and a low-level voltage (see Gout1 in figure 33) according to the voltage level of the first node (N3, fig. 17) and the voltage level of the second node (N2, fig. 17),
wherein a gate of the first transistor (T2, fig. 17), a gate of the second transistor (T4, fig. 17), and the gate of the third transistor (T5, fig. 17) is connected to the first clock terminal receiving the first clock signal (CLK1, [0226] The fifth control signal terminal K5 may be one of the plurality of clock signal terminals. Examiner’s Note: the plurality of clock signal terminals may include CLK1 as illustrated in fig. 17), wherein the first transistor and the second transistor are P-type transistors (T2 and T4 are p-type as seen in fig. 17 ), and wherein the third transistor is an N-type transistor (T5 is an n-type transistor as illustrated in fig. 17).
As to claim 9, Xu teaches the driving circuit of wherein each of the plurality of stages further comprises: a fourth transistor (T10, fig. 17) connected between the first transistor (T2, fig. 17) and the first node (N3, fig. 17) and comprising a gate connected to a terminal to which a first voltage of a low level is input (VGL, fig. 17).
As to claim 12, Xu teaches the driving circuit of wherein the output circuit comprises: a pull-down transistor (T16, fig. 17) connected between an output terminal (Gout1, fig. 17) and a clock terminal (s1, CLK4, fig. 17) and comprising a gate connected to the first node (N3, fig. 17); a pull-up transistor (T17, fig. 17) connected between a terminal to which a second voltage of a high level is supplied (VGH at s2, fig. 17) and the output terminal (Gout1, fig. 17) and comprising a gate connected to the second node (N2, fig. 17); and a capacitor (C4, fig. 17) connected between the first node (N3, fig. 17) and the output terminal (Gout1, fig. 17).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
4. Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Xu et al (US 2024/0379063) in view of Otose et al (US 2009/0290677).
As to claim 2, Xu does not teach the driving circuit as claimed.
However, Otose teaches the driving circuit of wherein the plurality of stages include a first stage (SR1, fig. 4), a last stage (SR4, fig. 4), and a plurality of intervening stages (SR2 and SR3, fig. 4) which are connected with each other in series (as seen in fig. 4), wherein the plurality of intervening stages are connected with each other in series and disposed between the first stage and the last stage, and wherein the first stage receives an external signal as the first signal (ST, fig. 4), and wherein each of the last stage and the plurality of intervening stages receives a corresponding gate signal, among the plurality of gate signals, output from a previous stage of the plurality of stages (fig. 4 illustrates that SR2 receives G1, SR3 receives G2, and SR4 receives G3).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Xu to teach the plurality of stages, as suggested by Otose. The motivation would have been in order improve the functionality of the shift register circuit by “exploiting a bootstrap effect” ([0008]).
5-8. (Canceled)
10. (Withdrawn)
11. (Withdrawn)
17-24. (Canceled)
Allowable Subject Matter
5. Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
6. Claims 13-16 are allowed.
The following is an examiner’s statement of reasons for allowance:
The prior art of record alone or in combination, fails to teach or render obvious, “A driving circuit comprising a plurality of stages that output a plurality of gate signals to a plurality of pixels, wherein each of the plurality of stages comprises: a first transistor connected between a first node and an input terminal to which a start signal is input and comprising a gate connected to a first clock terminal to which a first clock signal is input; a second transistor connected between a second node and a first voltage input terminal to which a first voltage of a low level is input and comprising a gate connected to the first clock terminal; a third transistor connected between the second node and a second voltage input terminal to which a second voltage of a high level is input and comprising a gate connected to the first clock terminal; and an output circuit connected to the second voltage input terminal and a second clock terminal to which a second clock signal is input and configured to output a corresponding gate signal, among the plurality of gate signals, of one of a high-level voltage and a low-level voltage according to a voltage level of the first node and a voltage level of the second node, and wherein the first transistor and the second transistor are P-type transistors, and the third transistor is an N-type transistor” in combination with the other claimed limitations set forth in claim 13.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AMEN W BOGALE whose telephone number is (571)270-1579. The examiner can normally be reached M-F 10:AM-6:PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Nitin Patel can be reached at (571)272-7677. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/AMEN W BOGALE/Examiner, Art Unit 2628
/NITIN PATEL/Supervisory Patent Examiner, Art Unit 2628
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