DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 03/03/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4-5, 8-10, and 20-23 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hisada (U.S. 2013/0070002) in view of Lee (U.S. 2014/0292622), and further in view of Kim (KR 2012012837).
As to claim 2, Hisada discloses a display device (abstract, [0066] (Fig. 1)) comprising: a first pixel (Fig. 8, (R)) comprising a first pixel circuit (Fig. 8, (525R)[0109] and a first light emitting element including a first pixel electrode (Fig. 8, (531R)[0105]; a second pixel (Fig. 8, B) comprising a second pixel circuit (Fig. 8, (525B)[0109] adjacent to the first pixel circuit in a first direction (Fig. 11), and a second light emitting element including a second pixel electrode(Fig. 8, (531B)[0105]; a third pixel (Fig. 8, (G) comprising a third pixel circuit (Fig. 8, (525R)[0109] adjacent to the second pixel circuit in the first direction (Fig. 11), and a third light emitting element including a third pixel electrode(Fig. 8, (531B)[0105]; a first data line (Fig. 1, (23p) electrically connected to the first pixel circuit Fig. 1, (11R) and extending in a second direction crossing the first direction Fig. 1,(vertical direction)[0004, 0071, 0077](one signal line for every pixel circuit horizontally) ; a second data line (Fig. 1, (23q)) adjacent to the first data line in the first direction (Fig. 1, (23p)(horizontally), electrically connected to the second pixel circuit (Fig, 1, (11G )and extending in the second direction (vertically) )[0004, 0071, 0077](one signal line for every pixel circuit horizontally); a third data line spaced apart from the second data line (Fig. 1, the data line to the right of data line (23q)) in the first direction (horizontally), electrically connected to the third pixel circuit Fig. 1, (11B), and extending in the second direction (vertically) )[0004, 0071, 0077](one signal line for every pixel circuit horizontally); wherein the first pixel electrode (Fig. 1, (11R) overlaps the first (fig. 1, (23p) and second data lines (Fig. 1, (23q)[0073], the second pixel electrode (Fig. 1, (G) is spaced apart from the first to third data lines on a plane (23p, 23q and third data line over (11B)[0073], and the third pixel electrode (Fig. 1, (11B) overlaps the third data line (Fig. 1, third data line, from left to right is overlapped by pixel electrode (Fig. 1, (11B))[0073].
Hisada, however, further, does not specifically disclose a driving voltage line between the second and third data lines, and electrically connected to at least one of the first to third pixel circuits.
Lee discloses a driving voltage line (Figs 6, (7)) between the second and third data lines (Fig. 6, second and third data lines (4) from left to right, have driving voltage line (7) between them), and electrically connected to at least one of the first to third pixel circuits (Figs. 6 and 7, (driving voltage line (7) is connected to pixel (2G)[0083-0085]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have modified the invention of Hisada to incorporate the teaching of Lee to configure a driving voltage line disposed between the data lines in order to provide voltage line functioning as a metal shield ([0085]).
Further, Hisada, as anticipated by Lee, does not specifically disclose the driving voltage line is disposed on a same layer as the first to third data lines.
Kim discloses the driving voltage line (Figs. 9 and 12, (PL) is disposed on a same layer as the first to third data lines (Figs. 9 and 12, (Dm-1, Dm, etc))(claims 4 and 9)(”the driving voltage line is formed on the same layer as the plurality of data lines”). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have the driving voltage line and the data lines on a same layer, as taught by Kim, in the device of Hisada and Lee, in order to reduce the need for additional cabling, reduces the need for additional layers which is more expensive, and thereby reduces the risk of signal interference.
As to claim 4, Hisada, further, does not specifically disclose the first pixel circuit comprises a thin film transistor electrically connected between the driving voltage line and the first pixel electrode.
Lee discloses the first pixel circuit [0064] comprises a thin film transistor (Fig. 5, (T1) electrically connected between the driving voltage line (Fig. 5, (7)) and the first pixel electrode (Fig. 5, (OLED). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have the connection, as taught by Lee, in Hisada, since this configuration is well known in the art of display devices in general, especially in LED displays, as to the driving TFT receiving power from a voltage line and driving the pixel electrode.
As to claim 5, Hisada discloses the first pixel emits red light (Fig. 1, (11R), the second pixel emits green light (Fig. 1, (11G), and the third pixel emits blue light (Fig. 1, (11B).
As to claim 8, Hisada, further, discloses the first pixel electrode (Fig. 2, (R) and the third pixel electrode (Fig. 2, (G) are disposed in a same row in plan view, and the second pixel electrode (Fig. 2, (B)is disposed in a different row from the first (R) and third pixel electrodes (G)in plan view (see Fig. 2).
As to claim 9, Hisada discloses the second pixel electrode (Fig. 2, (G) is disposed between the second data line (Fig. 2, 123q) and the third data line (Fig. 2, data line to the right of (G) in plan view.
As to claim 10, Hisada discloses a center portion of the first pixel electrode (Fig. 2, (center part of (R)) and a center portion of the third pixel electrode (Fig. 2, (center part of (B) does not overlap the driving voltage line in plan view (either voltage lines 123p or 123q are not being overlapped by the central portion of pixel electrodes (R and B).
As to claim 20, Hisada, further, discloses a distance between the first data line (Fig. 2, (123p) and the first pixel electrode (R) is shorter than a distance between the second data line (Fig. 2, (123q) and the second pixel electrode (G) in plan view (from left to right).
As to claim 21, Hisada, further, discloses a distance between the third data line (Fig. 2, data line (123p to the right of G) and the third pixel electrode (Fig. 2, (G) is shorter than a distance between the second data line (Fig. 2, (123q) and the second pixel electrode (B) in plan view (from left to right).
As to claim 22, Hisada, further, does not specifically disclose a part of the second portion and a part of the third portion of the driving voltage line are parallel.
Lee discloses However, Lee teaches: a driving voltage line (7 in Fig. 6 and 7) disposed between the plurality of data lines (4); and the driving voltage line (7) comprises: a first portion (VL corresponding to 2G) overlapping the second pixel electrode (120G in Fig. 6); a second portion (VL corresponding to 2R) extended from a first side of the first portion (Figs. 6 and 7; the HL extends between VL corresponding 2G and 2R) and overlapping the first pixel electrode (120R); and a third portion (VL corresponding to 2B) extended parallel to the second portion (VL corresponding to 2R) from a second side of the first portion (Figs. 6 and 7; the HL extends between VL corresponding 2G and 2B) and overlapping the third pixel electrode (120B).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified the invention of Hisada to incorporate the teaching of Lee and Kim to configure a driving voltage line disposed between the plurality of data lines; and to configure the driving voltage line to comprise: a first portion overlapping the second pixel electrode; a second portion extended from a first side of the first portion and overlapping the first pixel electrode; and a third portion extended parallel to the second portion from a second side of the first portion and overlapping the third pixel electrode. The motivation of combining these analogous arts is to provide voltage line functioning as a metal shield ([0085]).
As to claim 23, Hisada discloses the second data line (Fig. 2, (123q) and the third data line (Fig. 2, (123p to the right of G) are spaced apart from each other in the first direction (123p and second 123p to the right of G are space apart in the horizontal direction).
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hisada (U.S. 2013/0070002) in view of Lee (U.S. 2014/0292622), and Kim (KR 2012012837), as in claim 2, and further in view of Park (KR 20200077677).
As to claim 6, further, Hisada does not specifically disclose the first pixel circuit comprises: a first anode connection electrode electrically connected between the thin film transistor and first pixel electrode; and a first connection electrode electrically connected between the thin film transistor and the first anode connection electrode, wherein the first anode connection electrode is located on a same layer as the driving voltage line.
Lee discloses the first pixel circuit [0064, 0067] comprises: a first anode connection electrode [(0067, 0069] electrically connected between the thin film transistor (Fig. 5, (T1)) and first pixel electrode (Fig. 5, (OLED); and a first connection electrode (Fig. 5, T6)] electrically connected between the thin film transistor (Fig. 5, (T1) and the first anode connection electrode [0067, 0069]. Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have the connection, as taught by Lee, in Hisada, since this configuration is well known in the art of display devices in general, specially, in LED displays.
However, Hisada, as anticipated by Lee and Kim, does not disclose the first anode connection electrode is located on a same layer as the driving voltage line.
Park discloses the first anode connection electrode is located on a same layer as the driving voltage line(see claim 2). Therefore, it would have been obvious to one of ordinary skill in the art at the time of filing to have the anode electrode on the same layer as the driving voltage line, as taught by Park, in the device of Hisada and Lee, in order to reduce the need for additional cabling, reduces the need for additional layers which is more expensive, and thereby reduces the risk of signal interference.
Claim(s) 7 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hisada (U.S. 2013/0070002) in view of Lee (U.S. 2014/0292622), and Kim (KR 2012012837), as in claim 2, and further in view of Lee (2016/0155983, Lee ‘983, hereafter).
As to claim 7, Hisada, further teaches: wherein the third pixel electrode (B) is spaced apart from the first pixel electrode (R) in the first direction (see Fig. 2).
However, Hisada, as anticipated by Lee and Kim, further, does not specifically disclose the second pixel electrode is spaced apart from the first pixel electrode in an oblique direction with respect to the first direction and the second direction.
Lee ‘983 teaches: the second pixel electrode (G) is spaced apart from the first pixel electrode (R) in an oblique direction with respect to the first direction and the second direction (see Fig. 4).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified the invention of the combination of Hisada, Lee, and Kim, to incorporate the teaching of Lee ‘983 to configure the second pixel electrode to be spaced apart from the first pixel electrode or the third pixel electrode in an oblique direction with respect to the first direction and the second direction. The motivation of combining these analogous arts is to increase outside visibility and a contrast ratio of a screen by minimizing reflection of external light by a metal reflective film such as a pixel electrode ([0008]).
As to claim 19, Hisada, as anticipated by Lee and Kim, does not specifically disclose a substrate; a thin film transistor disposed on the substrate; a passivation layer covering the thin film transistor; and a planarization layer disposed on the passivation layer, wherein the first and second data lines are disposed on the passivation layer, and the first to third pixel electrodes are disposed on the planarization layer.
Lee ‘983, in Fig. 7, teaches: a substrate (110); a thin film transistor (T1-T6) disposed on the substrate (110); a passivation layer (160) covering the thin film transistor (T1-T6); and a planarization layer (180) disposed on the passivation layer (160), wherein the first and second data lines (171) are disposed on the passivation layer (160), and the first to third pixel electrodes (191) are disposed on the planarization layer (180).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to have modified the invention of the combination of Hisada, Lee and Kim,to incorporate the teaching of Lee ‘983 to configure a substrate; a thin film transistor disposed on the substrate; a passivation layer covering the thin film transistor; and a planarization layer disposed on the passivation layer, wherein the first and second data lines are disposed on the passivation layer, and the first to third pixel electrodes are disposed on the planarization layer. The motivation of combining these analogous arts is to increase outside visibility and a contrast ratio of a screen by minimizing reflection of external light by a metal reflective film such as a pixel electrode ([0008]).
Allowable Subject Matter
Claims 3, and 11-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claims 3, and 11-18 are indicated as allowable since, certain key features of the claimed invention are not taught or fairly suggested by the prior art. In claim 1, “the driving voltage line comprises: a first portion overlapping the second pixel electrode between the second data line and the third data line; a second portion branched from the first portion and overlapping the first pixel electrode between the second data line and the third data line; and a third portion branched from the first portion and overlapping the third pixel electrode between the second data line and the third data line, a part of the second portion and a part of the third portion of the driving voltage line are parallel“. In claim 11, “a first coupling capacitor connected between the first data line and a fourth node, which is connected to the first pixel electrode”. The closest prior art of record, Lee (US 2014/0292622), discloses, regarding claim 3, a driving voltage line (7 in Fig. 6 and 7) disposed between the plurality of data lines (4); and the driving voltage line (7) comprises: a first portion (VL corresponding to 2G) overlapping the second pixel electrode (120G in Fig. 6); a second portion (VL corresponding to 2R) extended from a first side of the first portion (Figs. 6 and 7; the HL extends between VL corresponding 2G and 2R) and overlapping the first pixel electrode (120R); and a third portion (VL corresponding to 2B) extended parallel to the second portion (VL corresponding to 2R) from a second side of the first portion (Figs. 6 and 7; the HL extends between VL corresponding 2G and 2B) and overlapping the third pixel electrode (120B). Also, Lee (US 2014/0292622) discloses, regarding claim 11, in Fig. 5, a first transistor (T1) which controls a driving current flowing through the first pixel electrode (OLED); a second transistor (T2) which supplies a data voltage (Dm) to a first node, which is connected to a source electrode of the first transistor (T1, (S1)); a third transistor (T3) which connects a second node, which is connected to a drain electrode of the first transistor (T1, (D1)), to a third node, which is connected to a gate electrode of the first transistor (T1, (G1). However, singularly or in combination, fails to anticipate or render the above underlined limitations obvious, together with all the other limitations of the claims.
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/RICARDO OSORIO/Primary Examiner, Art Unit 2625