DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6 and 9-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Han et al. (U.S. Patent No. 10,164,150).
Regarding claim 1, Han discloses a light emitting element that emits an ultraviolet ray (Fig. 8, Fig. 12, column 9, lines 54-55), the light emitting element comprising:
an n-type layer comprising an n-type group III nitride semiconductor containing Al (Fig. 8, element 27; Fig. 12, element 127, column 8, lines 11-12);
an active layer located over the n-type layer, comprising a group III nitride semiconductor containing Al (Fig. 8, element 39; Fig. 12, element 139, column 9, lines 47-50), and having a quantum well structure including a well layer (Fig. 8, element 39w; Fig. 12, element 139w, column 9, lines 52-53) and a barrier layer (Fig. 8, element 39b/39b1; Fig. 12, element 139b, column 9, lines 65-66); and
a p-type layer located over the active layer and comprising a p-type group III nitride semiconductor containing Al (Fig. 8, element 43; Fig. 12, element 143, column 18, lines 13-14), wherein
the barrier layer comprises
a first barrier layer non-doped or doped with an n-type impurity (Fig. 8, element 39b; column 10, lines 60-62, first barrier layer is undoped), and
a second barrier layer located over the first barrier layer, being in contact with a surface of the well layer at a side of the n-type layer (Fig. 8, element 39b1; column 10, lines 11-13, lines 32-34), and doped with an n-type impurity at a concentration higher than a concentration of the n-type impurity doped in the first barrier layer (column 10, lines 8-10, n-doped with concentration closed to of the n-type contact layer 27).
Regarding claim 2, Han discloses an uppermost barrier layer, which is a layer closest to the p-type layer among layers included in the barrier layer, is a non-doped group III nitride semiconductor (column 10, lines 60-62, all barrier layers 39b are undoped including the uppermost barrier layer).
Regarding claim 3, Han discloses the first barrier layer is non-doped (column 11, lines 60-62, first barrier layer 39b is undoped), and the second barrier layer has a Si concentration of 1 x 1018 cm-3 to 2 x 1019 cm-3 (column 10, lines 8-10, n-doped with concentration closed to concentration of the n-type contact layer 27; column 8, lines 26-29, layer 27 is n-doped with silicon dopant at concentration from 1 x 1018 cm-3 to 2 x 1019 cm-3).
Regarding claim 4, Han discloses the first barrier layer is non-doped (column 11, lines 60-62, first barrier layer 39b is undoped), and the second barrier layer has a Si concentration of 1 x 1018 cm-3 to 2 x 1019 cm-3 (column 10, lines 8-10, n-doped with concentration closed to of the n-type contact layer 27; column 8, lines 26-29, layer 27 is n-doped with silicon dopant at concentration from 1 x 1018 cm-3 to 2 x 1019 cm-3).
Regarding claim 5, Han discloses the first barrier layer has a thickness of 2 nm to 20 nm, and the second barrier layer has a thickness of 2 nm to 20 nm (column 10, lines 53-55, 40A is 4 nm).
Regarding claim 6, Han discloses the first barrier layer has a thickness of 2 nm to 20 nm, and the second barrier layer has a thickness of 2 nm to 20 nm (column 10, lines 53-55, 40A is 4 nm).
Regarding claim 9, Han discloses a superlattice layer located between then-type layer and the hole blocking layer so that the superlattice layer is in contact with the hole blocking layer, and formed by alternately stacking group III nitride semiconductors having different Al compositions (Fig. 8, element 35; Fig. 12, element 135, column 16, lines 28-31).
Regarding claim 10, Han discloses a superlattice layer located between then-type layer and the hole blocking layer so that the superlattice layer is in contact with the hole blocking layer, and formed by alternately stacking group III nitride semiconductors having different Al compositions (Fig. 8, element 35; Fig. 12, element 135, column 16, lines 28-31).
Regarding claim 11, Han discloses the active layer has an MQW structure (column 9, lines 47-50).
Regarding claim 12, Han discloses the active layer has an MQW structure (column 9, lines 47-50).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U.S. Patent No. 10,164,150), as applied to claim 1 above, in view of Fudeta et al. (U.S. Patent No. 9,070,805).
Regarding claim 7, Han discloses a layer located between the n-type layer and the active layer so that the layer is in contact with the active layer, and comprising AlGaN or AlN having an Al composition higher than an Al composition in the barrier layer (Fig. 8, element 37; Fig. 12, element 137, column 17, lines 1-3). Han does not disclose the layer is configured as a hole blocking layer. Fudeta discloses the layer between the n-type layer and the active layer, above the superlattice layer, so that the layer is in contact with the active layer, is configured to be a hole blocking layer (column 8, lines 53-54, layer 13 between n-type layer 9 and active layer 15, above superlattice layer 11, is configured to be a hole blocking layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Han in view of Fudeta to configure the layer between the n-type layer and the active layer so that the layer is in contact with the active layer, to be a hole blocking layer, in order to promote electron movement while preventing hole movement, thus to increase efficiency.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Han et al. (U.S. Patent No. 10,164,150), as applied to claim 1 and claim 2 above, in view of Fudeta et al. (U.S. Patent No. 9,070,805).
Regarding claim 8, Han discloses a layer located between the n-type layer and the active layer so that the layer is in contact with the active layer, and comprising AlGaN or AlN having an Al composition higher than an Al composition in the barrier layer (Fig. 8, element 37; Fig. 12, element 137, column 17, lines 1-3). Han does not disclose the layer is configured as a hole blocking layer. Fudeta discloses the layer between the n-type layer and the active layer, above the superlattice layer, so that the layer is in contact with the active layer, is configured to be a hole blocking layer (column 8, lines 53-54, layer 13 between n-type layer 9 and active layer 15, above superlattice layer 11, is configured to be a hole blocking layer). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Han in view of Fudeta to configure the layer between the n-type layer and the active layer so that the layer is in contact with the active layer, to be a hole blocking layer, in order to promote electron movement while preventing hole movement, thus to increase efficiency.
Pertinent Art
For the benefits of the Applicant, US-8604461-B2, US-11476391-B2, US-12389716-B2, US-11404603-B2, US-6958497-B2, US-6838705-B1, US-11984526-B2, US-6337493-B1, US-12615884-B2, and US-8536615-B1, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. In particular, references fail to disclose the barrier layer comprises a first barrier layer non-doped or doped with an n-type impurity, and a second barrier layer located over the first barrier layer, being in contact with a surface of the well layer at a side of the n-type layer, and doped with an n-type impurity at a concentration higher than a concentration of then-type impurity doped in the first barrier layer.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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