Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 9/17/2024 and 08/15/2025 was filed after the mailing date of the first action on the merits. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Double Patenting
Claims 1-20 are rejected on the ground of non-statutory double patenting as being unpatentable over claims 1-23 of U.S. Patent No. 12,120,876. Although the claims at issue are not identical, they are not patentably distinct from each other because similar subject matter is claimed:
‘876
A semiconductor device, comprising:
a first semiconductor structure including a first substrate, circuit elements on the first substrate, and lower interconnection lines; and
a second semiconductor structure on the first semiconductor structure,
wherein the second semiconductor structure includes
a second substrate having a first region and a second region,
gate electrodes stacked on the second substrate to be spaced apart from each
other in a first direction, the gate electrodes at least partially defining first and second stack structures,
interlayer insulating layers alternately stacked with the gate electrodes,
channel structures penetrating through the first and second stack structures,
the channel structures extending in the first direction, the channel structures
respectively including a channel layer, the channel structures being in the first region,
separation regions penetrating through the first and second stack structures
and extending in a second direction,
first and second contact plugs each penetrating through the first and second
stack structures and extending into the first semiconductor structure in the first
direction, the first and second contact plugs being in the second region, and
contact insulating layers in contact with portions of the gate electrodes and
surrounding each of the first and second contact plugs, the contact insulating layers being in the second region,
wherein the first stack structure has, in the second region,
first pad areas in which the gate electrodes extend further than upper gate
electrodes, respectively, in the second direction to be connected to the first contact plugs, respectively, and
first dummy areas located on at least one side of each of the first pad areas and spaced apart from the first contact plugs,
wherein the second stack structure has, in the second region,
second pad areas in which the gate electrodes extend further than upper gate
electrodes, respectively, in the second direction and connected to the second contact plugs, respectively, and
second dummy areas located on at least one side of each of the second pad
areas and spaced apart from the second contact plugs, and
wherein the first pad areas overlap the second dummy areas in the first direction, and
the second pad areas overlap the first dummy areas in the first direction.
Instant application:
1. A semiconductor device, comprising:
a first semiconductor structure including a first substrate, circuit elements on the first substrate, and lower interconnection lines; and
a second semiconductor structure on the first semiconductor structure, wherein the second semiconductor structure includes
a second substrate having a first region and a second region,
first and second stack structures vertically stacked on the second substrate, each of the first and second stack structures including gate electrodes stacked to be spaced apart from each other in a first direction,
channel structures penetrating through the first and second stack structures, the channel structures being in the first region, and
first and second contact plugs each penetrating through the first and second stack structures and extending into the first semiconductor structure in the first direction, the first and second contact plugs being in the second region, and wherein the first stack structure has, in the second region,
first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in a second direction to be connected to the first contact plugs in first contact regions, respectively, and
first dummy areas located on at least one side of each of the first pad areas and spaced apart from the first contact plugs, wherein the second stack structure has, in the second region,
second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in the second direction to be connected to the second contact plugs in second contact regions, respectively, and
second dummy areas located on at least one side of each of the second pad areas and spaced apart from the second contact plugs, and
wherein in each of the first pad areas, at least two of the first contact regions have different lengths in the second direction.
‘876
18. A semiconductor device, comprising: a first substrate; circuit elements on the first substrate; lower interconnection lines electrically connected to the circuit elements; a second substrate on the lower interconnection lines;
gate electrodes stacked on the second substrate to be spaced apart from each other in a first direction, the gate electrodes at least partially defining first and second stack structures;
channel structures penetrating through the gate electrodes, the channel structures extending in the first direction, the channel structures respectively including a channel layer; and
first and second contact plugs each penetrating through the first and second stack structures, the first and second contact plugs being connected to the gate electrodes, respectively, the first and second contact plugs extending in the first direction,
wherein the first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in a second direction and are connected to the first contact plugs, respectively,
wherein the second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in the second direction and are connected to the second contact plugs, respectively, and
wherein the first pad areas and the second pad areas are offset in relation to each other so as not to overlap each other in the first direction.
Instant:
15. A semiconductor device, comprising: a substrate;
first and second stack structures vertically stacked on the substrate, each of the first and second stack structures including gate electrodes stacked to be spaced apart from each other in a first direction;
channel structures penetrating through the gate electrodes; and
first and second contact plugs each penetrating through the first and second stack structures, the first and second contact plugs being connected to the gate electrodes, respectively, the first and second contact plugs extending in the first direction,
wherein the first stack structure has first pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in a second direction to be connected to the first contact plugs in first contact regions, respectively,
wherein the second stack structure has second pad areas in which the gate electrodes extend further than upper gate electrodes, respectively, in the second direction to be connected to the second contact plugs in second contact regions, respectively;
wherein at least two of the first contact regions have different lengths in the second direction, and
wherein each contact plug of the first and second contact plugs includes,
a vertical extension portion extending in the first direction, and
a horizontal extension portion extending horizontally from the vertical extension portion, to contact an uppermost gate electrode in one pad area of the first and second pad areas.
The difference between the two sets of independent claims is that the patented claims claim overlapping pad areas, while the instant application claims different lengths for the contact regions. It would have been obvious to one of ordinary skill in the art to form contact regions with different lengths, because the first and second pad areas have different spacings.
Note: Dependent claims not repeated for brevity of office action.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL LEBENTRITT whose telephone number is (571)272-1873. The examiner can normally be reached IFP Mon- Fri 8:30 am- 6 pm.
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MICHAEL . LEBENTRITT
Primary Examiner
Art Unit 2893
/MICHAEL LEBENTRITT/Primary Examiner, Art Unit 2893
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