Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to application No. 18887709 filed on 09/17/2024.
Information Disclosure Statement
Acknowledgment is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Sekiya et al. (CN 102842494 A) in view of Glenn et al. (US 6309943 B1).
Regarding independent claim 1, Sekiya et al. teach a method of processing a wafer,
the wafer (fig. 1, element 11 [0047]) including on a side of a front surface (fig. 1, element 11a [00 ])
a plurality of intersecting planned dividing lines (fig. 1, elements 13a & 13b [0047])
and a plurality of devices (fig. 1, element 17 [0048]) formed in respective areas (fig. 1) defined by the planned dividing lines (fig. 1),
and a metal layer (fig. 4, element 18 [0057]) laminated on a side of a back surface (fig. 4, element 11b [0052]),
Sekiya et al. do not explicitly teach the method comprising: forming a mark indicating positions of the planned dividing lines of the wafer on the back surface;
and dicing the wafer from the side of the back surface using the formed mark as a reference to divide the wafer into individual chips.
However, Glenn et al. is a pertinent art which teaches forming a mark (fig. 5A, elements 462A, 462B, 462C, 462D [column 7 line 40]) indicating positions of the planned dividing lines (fig. 3, element 316 [column 4 line 50]) of the wafer on the back surface (fig. 5A, element 310B [column 4 line 50]);
and dicing the wafer ([column 8 lines 35-45]) from the side of the back surface ([column 8 lines 50-55]) using the formed mark as a reference to divide the wafer into individual chips (fig. 3, element 312 [column 4 line 65]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of processing a wafer of Sekiya et al. as taught by Glenn et al. in order to employ the alignment mark to control stepping of the saw blade during singulation, e.g., to prevent the saw blade from stepping off of wafer during singulation ([column 7 line 50]) and cut the wafer from back-side surface without the associated loss of yield of the prior art. As a result, integrated circuits of wafer are protected during singulation yet are fabricated without the associated substantial increase in cost of the prior art ([column 9 lines 50-55]).
Regarding claim 2, Sekiya et al. as modified by Glenn et al. teach the method of processing a wafer, wherein,
forming the mark includes holding the side of the front surface (figs. 4, 10 of Sekiya et al.) of the wafer by a holding table (fig. 5 of Sekiya et al. element 31 [0060]) including a holding surface (fig. 10 of Sekiya et al. element 21 [0049]) at least a part of which is made of a transparent material ([0049] of Sekiya et al.),
and capturing an image (fig. 5 of Sekiya et al. element 35 [0062]) of the side of the front surface of the wafer through the holding surface to detect the planned dividing lines ([0066] of Sekiya et al.),
the mark being formed based on the detected planned dividing lines ([column 7 line 40] of Glenn et al.).
Regarding claim 3, Sekiya et al. modified by Glenn et al. teach the method of processing a wafer, wherein,
wherein the mark is formed in an area that corresponds to the planned dividing lines ([column 7 line 40] of Glenn et al.) and is to be removed in dicing the wafer ([column 4 lines 45-65] of Glenn et al.).
Regarding claim 4, Sekiya et al. as modified by Glenn et al. teach the method of
processing a wafer, wherein
the mark is formed in a cross shape (fig. 5A of Glenn et al.) and is formed in an area that corresponds to an intersection (figs. 3 & 5A of Glenn et al.) of the planned dividing lines and is to be removed in dicing the wafer ([column 4 lines 45-65] of Glenn et al.).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Sekiya et al. (CN 102842494 A) in view of Glenn et al. (US 6309943 B1) and further in view of Haimoto et al. (KR 20220072739 A)
Regarding claim 5, Sekiya et al. as modified by Glenn et al. teach all the limitations as discussed above,
Sekiya et al. as modified by Glenn et al. do not explicitly teach the wafer is made of SiC.
However, Haimoto et al. is a pertinent art which teaches the wafer is made of SiC ([technical field]).
Therefore, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to modify the method of processing a wafer of Sekiya et al. and Glenn et al. as taught by Haimoto et al. to employ SiC wafer in order to use in plurality of devices such as power devices and LEDs and in electric devices such as automobile control devices and personal computers ([background-art]).
Cited Prior Art
The Examiner has pointed out particular references contained in the prior art of record within the body of this action for the convenience of the Applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ARIFUR RAHMAN whose telephone number is (571) 895-1534. The examiner can normally be reached on Monday-Friday, 9:00 AM - 5:00 PM (Eastern Time). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, GAUTHIER STEVEN B, can be reached on (571) 270-0373. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at (866) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call (800) 786-9199 (IN USA OR CANADA) or (571) 272-1000.
/ARIFUR RAHMAN/
Examiner, Art Unit 2813
/SHAHED AHMED/Primary Examiner, Art Unit 2813
