Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
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Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US Pub # 2018/0203796).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding independent claim 1, Park et al. teach a method of operating a memory device, comprising the steps of: preparing a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being segmented into a first sub-block and a second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, memory array 110 where wordlines are segmented for first and second plane PLA1 and PLA2 into section); receiving a programming command for the first sub-block; applying a reference voltage to a plurality of word lines of the second sub-block; performing a sensing operation on the plurality of word lines of the second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, program operation PGM for section 1-PLA1 and sensing operation BL_SEN for section1-PLA2); and based on results of the sensing operation, establishing whether the second sub-block contains programmed memory cells or does not contain programmed memory cells (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, sensing operation determined where programmed or not).
Even though Park et al. teach sections / subblock for each plane / block but silent exclusively about word lines being segmented into a first sub-block and a second sub-block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Park et al. where independent operation like program, sensing operation are done for each section of the plane i.e. word lines of the plane must be segmented for each section or sub-block in order to effectively control the operation and to detect power noise that occurs during an operation of some areas from among a plurality of memory areas and control an operation of the remaining memory areas among the plurality of memory areas (see paragraph 0166).
Regarding claim 2, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein the step of applying the reference to the plurality of word lines of the second sub-block includes applying the reference voltage to all of the word lines of the second sub-block block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131).
Regarding claim 3, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein during the sensing operation, no word lines receive a pass voltage VREAD (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0145).
Regarding claim 4, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the sensing operation is performed on only a single one of the plurality of strings (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126).
Regarding claim 5, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the sensing operation is simultaneously performed on all of the plurality of strings (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140).
Regarding claim 6, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein the sensing operation includes discharging at least one sense amplifier through at least one NAND string of the memory block and determining a discharge current through the at least one NAND string (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0147).
Regarding claim 7, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein the step of establishing whether the second sub-block contains programmed memory cells or does not contain programmed memory cells includes comparing the discharge current to a predetermined threshold (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0149).
Regarding claim 8, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, further including the step of applying a VPVD voltage that is greater than the reference voltage to a plurality of word lines of the first sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0139).
Regarding independent claim 9, Park et al. teach a memory device, comprising: a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being segmented into a first sub-block and a second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, memory array 110 where wordlines are segmented for first and second plane PLA1 and PLA2 into section); circuitry that is configured to; receive a programming command for the first sub-block; apply a reference voltage to a plurality of word lines of the second sub-block; perform a sensing operation on the plurality of word lines of the second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, program operation PGM for section 1-PLA1 and sensing operation BL_SEN for section1-PLA2); and based on results of the sensing operation, establish whether the second sub-block contains programmed memory cells or does not contain programmed memory cells (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, sensing operation determined where programmed or not).
Even though Park et al. teach sections / subblock for each plane / block but silent exclusively about word lines being segmented into a first sub-block and a second sub-block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Park et al. where independent operation like program, sensing operation are done for each section of the plane i.e. word lines of the plane must be segmented for each section or sub-block in order to effectively control the operation and to detect power noise that occurs during an operation of some areas from among a plurality of memory areas and control an operation of the remaining memory areas among the plurality of memory areas (see paragraph 0166).
Regarding claim 10, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the circuitry is configured to apply the reference voltage to all of the word lines of the second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0138).
Regarding claim 11, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein during the sensing operation, the circuitry does not apply a pass voltage VREAD to any of the word lines (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140).
Regarding claim 12, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the circuitry is configured to perform the sensing operation only a single one of the plurality of strings (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0148).
Regarding claim 13, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the circuitry is configured to perform the sensing operation on all of the plurality of strings simultaneously (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0150).
Regarding claim 14, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the sensing operation includes the circuitry discharging at least one sense amplifier through at least one NAND string of the memory block and determining a discharge current through the at least one NAND string (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0145).
Regarding claim 15, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein when determining whether the second sub-block contains programmed memory cells or does not contain programmed memory cells, the circuitry compares the discharge current to a predetermined threshold (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0139).
Regarding claim 16, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the circuitry is further configured to apply a VPVD voltage that is greater than the reference voltage to a plurality of word lines of the first sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143).
Regarding independent claim 17, Park et al. teach an apparatus, comprising: a memory block that includes an array of memory cells that are arranged in a plurality of word lines, the plurality of word lines being segmented into a first sub-block and a second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, memory array 110 where wordlines are segmented for first and second plane PLA1 and PLA2 into section); a programming means for programming the array of memory cells of the memory block, the programming means being configured to; receive a programming command for the first sub-block; apply a reference voltage to all of the word lines of the second sub-block and apply a VPVD voltage to all of the word lines of the first sub-block; perform a sensing operation on all of the word lines of the second sub-block (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, program operation PGM for section 1-PLA1 and sensing operation BL_SEN for section1-PLA2); and based on results of the sensing operation, establish whether the second sub-block contains programmed memory cells or does not contain programmed memory cells (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0151, sensing operation determined where programmed or not).
Even though Park et al. teach sections / subblock for each plane / block but silent exclusively about word lines being segmented into a first sub-block and a second sub-block. However, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention was made to apply the teaching of Park et al. where independent operation like program, sensing operation are done for each section of the plane i.e. word lines of the plane must be segmented for each section or sub-block in order to effectively control the operation and to detect power noise that occurs during an operation of some areas from among a plurality of memory areas and control an operation of the remaining memory areas among the plurality of memory areas (see paragraph 0166).
Regarding claim 18, Park et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Park et al. further teach, wherein during the sensing operation, the programming means does not apply a pass voltage VREAD to any of the word lines and does not perform a VREAD spike operation (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0149).
Regarding claim 19, Park et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the programming means is configured to perform the sensing operation only a single one of the plurality of strings (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0150).
Regarding claim 20, Park et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Park et al. further teach, wherein the memory block includes a plurality of strings and wherein the programming means is configured to perform the sensing operation all of the plurality of strings simultaneously (see Fig. 1-3, 11-14, 16-18, paragraph 0033-0047, 0059-0064,0108-0116, 0119-0126, 0131-0140, 0143-0148).
Regarding claim 21, Park et al. teach all claimed subject matter as applied in prior rejection of claim 1 on which this claim depends.
Park et al. further teach, wherein, before programming begins on the first
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sub-block, the applying of the reference voltage, the performing of the sensing operation, and the establishing whether the second sub-block contains programmed memory cells or does not contain programmed memory cells are performed as a pre-read operation on the second sub-block (see Fig. 16-17, paragraph 0131-0151, pre-read operation done for sub-block 1 at step 4, VFY is reference voltage both for first and second sub-block).
Regarding claim 22, Park et al. teach all claimed subject matter as applied in prior rejection of claim 9 on which this claim depends.
Park et al. further teach, wherein the circuitry is configured to, before programming begins on the first sub-block, perform a pre-read operation on the second sub-block, the pre-read operation including applying the reference voltage, performing the sensing operation, and establishing whether the second sub-block contains programmed memory cells or does not contain programmed memory cells (see Fig. 16-17, paragraph 0131-0151, first sensing operation for second sub-block would be called pre-read operation).
Regarding claim 23, Park et al. teach all claimed subject matter as applied in prior rejection of claim 17 on which this claim depends.
Park et al. further teach, wherein the programming means is configured to, before programming begins on the first sub-block, perform a pre-read operation on the second sub-block, the pre-read operation including applying the reference voltage, performing the sensing operation, and establishing whether the second sub-block contains programmed memory cells or does not contain programmed memory cells (see Fig. 16-17, paragraph 0131-0151).
Response to Arguments
Applicant's arguments filed 06/10/2026 have been fully considered but they are not persuasive.
Applicant argues (see page 9 of remarks) that Park's disclosure does not teach the claimed memory block whose word lines are segmented into first and second sub-blocks". Examiner respectfully disagrees with this statement.
First, the claim limitations clearly indicate that memory block includes an array of memory cells and divided into first sub-block and second sub-block.
Second, The limitation “a memory block” and “an array” also indicate that memory array can also be a block and divided into two sub-block.
In Fig. 1-2, paragraph 0033-0034, 0042-0043, 0048 where Park et al. teach memory array would be divided into two or more plane i.e. whole array can have one block divided into two subblock / plane or array can be divided into multiple block and then further divided into subblock / plane. As the claim limitation is very broad and didn’t further specify block / sub-block, plane 111 and 122 would be called sub-block arranged in a block which includes an array of cells. In Fig.1, wordline WL is coupled to array / block 110 and the block is divided into two plane or sub-block 111, 122 where the global wordline WL is segmented into two local wordline.
Applicant argues (see page 9 of remarks) that the applied Park reference also does not teach applying a reference voltage to word lines of a second sub-block and then determining, based on a sensing operation of that second sub-block, whether the second sub-block contains programmed memory cells or does not contain programmed memory cells, as also required in amended claim 1". Examiner respectfully disagrees with this statement.
First, The sensing operation for second sub-block confirm whether cells were programmed or not even though it was never been programmed. This clearly indicates that second sub-block would be affected by the program command applied for the first sub-block i.e. second block is victim due to operation of first block.
Second, Even though the limitation indicate sensing operation for second sub-block, it is not limited to second section only as the claim limitation didn’t specify it. Similarly, receiving program command may not be only for first sub-block as the limitation didn’t indicate only for first sub-block.
In Fig. 16-18, paragraph 0131-0151, Park et al. teach programming operation at step S110 and sensing operation at step S120 (also see Fig. 16-17, program step 3 for PLA1, sensing step (II) for PLA2). During sensing step, reference voltage was applied for sensing operation (see specially paragraph 0007, 0037, 0046, 0131 where verification voltage is reference voltage applied for sensing operation). Here, sensing operation for second sub-block confirms victim section or programmed section due to program operation of first sub-block (noise section).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED A BASHAR whose telephone number is 469-295-9277 and fax number is (571)273-2908. The examiner can normally be reached on 9am-5pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard T Elms can be reached on 5712721869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MOHAMMED A BASHAR/Primary Examiner, Art Unit 2824
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