DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 4, 10, 12, 21 – 24 and 27 – 28 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Das et al. (US 2008/0296771).
(Claim 1) Das et al. teach a method of fabricating an integrated circuit, the method comprising:
providing a composite substrate (fig. 7A) having a top substrate layer (120) comprising single crystal silicon carbide and a bottom substrate layer comprising polycrystalline silicon carbide (paragraph 34);
epitaxially growing an active layer (720, paragraph 48) on the top substrate layer;
forming an active device (fig. 7B #734) in and on the active layer (720);
bonding a handle (fig. 7C #210, paragraph 50) to a top surface of the active device; and
removing the bottom substrate layer (fig. 7D, paragraph 51).
(Claim 2) Das et al. teach wherein the active device is a vertical insulated gate bipolar transistor (paragraph 34).
(Claim 3) Das et al. teach wherein the active device is a vertical MOSFET (paragraph 34).
(Claim 4) Das et al. teach wherein the active device comprises a silicon carbide layer.
(Claim 10) wherein:
the active device has a gate region, a source region, a drain region, and a channel region (fig. 7F); and
the channel region (732) is disposed below the gate region (734) and between the source region (752) and the drain region (710).
(Claim 12) Das et al. teach wherein the active device is a vertical transistor device, a vertical bipolar device, or a vertical unipolar device (paragraph 34).
(Claim 21) Das et al. teach a method of fabricating an integrated circuit, the method comprising:
providing a composite substrate having a top substrate layer (120) comprising single crystal silicon carbide and a bottom substrate layer (110) comprising a sacrificial material operable to form a structural support for integrated circuit device formation;
forming a single crystal transition layer (710) on the top substrate layer (120);
epitaxially growing an active layer (720) on the single crystal transition layer;
forming an active device (734) in and on the active layer;
bonding a handle (210, paragraph 50) to a top surface of the active device; and
removing the bottom substrate layer (fig. 7D, paragraph 51).
(Claim 22) Das et al. teach wherein the single crystal transition layer (710) comprises n-type or p-type SiC.
(Claim 23) wherein the single crystal transition layer comprises n-type Ga2O3.
(Claim 24) Das et al. teach wherein the handle comprises polycrystalline SiC, sintered ceramic, alumina, refractory metal, BN, graphite, or diamond-like material (paragraph 37).
(Claim 27) Das et al. teach wherein the bottom substrate layer is chemically or mechanically removed to expose a back surface of the top substrate layer (fig. 7D, paragraph 51).
(Claim 28) Das et al. teach wherein the back surface of the top substrate layer is configured for subsequent formation of an ohmic contact region on the back surface (fig. 7E, paragraph 52).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 5, 15 – 20 are rejected under 35 U.S.C. 103 as being unpatentable over Das et al. (US 2008/0296771) in view of Sagawa et al. (JP 2022-186426).
(Claim 5) Das et al. lack wherein the active device comprises a gallium oxide layer.
However, Sagawa teaches wherein the active device comprises a gallium oxide layer as art recognized equivalents and for the benefit of reducing cost (2nd paragraph under [Description of Embodiments of the Present Disclosure]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents and for the benefit of reducing cost.
(Claim 15) Das et al. teach a method of fabricating an integrated circuit, the method comprising:
providing a substrate (110/120/710) comprising single crystal silicon carbide (paragraph 48);
epitaxially growing an active layer (fig. 7B #720) on the substrate,
forming an active device (7B #734) in and on the active layer;
bonding a handle (fig. 7C #210) to a top surface of the active device; and
removing at least a portion of the substrate from a backside of the integrated circuit (paragraph 51).
Das et al. lack wherein the active layer comprises an oxide.
However, Sagawa teaches wherein the active layer comprises an oxide as art recognized equivalents and for the benefit of reducing cost (2nd paragraph under [Description of Embodiments of the Present Disclosure]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents and for the benefit of reducing cost.
(Claim 16) Das et al. teach wherein the active device is a vertical insulated gate bipolar transistor (paragraph 34).
(Claim 17) Das et al. teach wherein the active device is a vertical MOSFET (paragraph 34).
(Claim 18) Das et al. teach the method, further comprising:
forming channel regions (732) by a first ion implantation into the active layer;
forming source regions (752) by a second ion implantation into the active layer;
forming a drift region (720) in the active layer; and
forming a drain region (710) at the backside of the integrated circuit (paragraph 38).
(Claim 19) Das et al. lack wherein the oxide is gallium oxide.
However, Sagawa teaches wherein the oxide is gallium oxide as art recognized equivalents and for the benefit of reducing cost (2nd paragraph under [Description of Embodiments of the Present Disclosure]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the references as art recognized equivalents and for the benefit of reducing cost.
(Claim 20) Das et al. teach wherein:
the substrate (110/120/710) is a composite substrate having a first portion (110) and a second portion (120/710) formed on top of the first portion;
the first portion comprises polycrystalline silicon carbide (paragraph 48);
the second portion comprises the single crystal silicon carbide (paragraph 48); and
the removing of at least a portion of the substrate removes most or all of the first portion (110) of the substrate (paragraph 51).
Allowable Subject Matter
Claims 6 – 9, 11, 13 – 14, 25 and 26 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to IGWE U ANYA whose telephone number is (571)272-1887. The examiner can normally be reached 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at (571) 272- 1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/IGWE U ANYA/Primary Examiner, Art Unit 2891
September 11, 2026
