Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) was submitted on 09/17/2024. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to because figure 1 is described as showing capping layer 110 but the numeral 110 is not shown in figure 1. Numeral 110 is shown in other figures and the layer connected to the numeral 110 is present in figure 1, but the numeral 110 is missing from figure 1 and should be present as the specification includes numeral 110 being shown in figure 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The specification in paragraph [0028] states figure 1 includes capping layer 110, but capping layer 110 is not present in figure 1. Either paragraph [0028] should be corrected to remove capping layer 110 from figure 1, or figure 1 should be corrected to show numeral 110 representing the capping layer as stated in paragraph [0028]. See drawing objection above.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 2, and 5 – 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20150236121 A1 hereinafter Chiu in further view of US 10014402 B1 hereinafter Chen with evidence from Properties of Silicon Dioxide (SiO2) and Silicon Nitride (Si3N4) from EESemi and Resistivity and Conductivity - Temperature Coefficients Common Material from Engineering Tool Box.
For claim 1, Chiu teaches a method of fabricating a high electron mobility transistor, comprising: providing a substrate (Chiu, fig. 3I numeral 102) having a semiconductor channel layer (fig. 3I numeral 108), a semiconductor barrier layer (fig. 3I numeral 110), a semiconductor capping layer (fig. 3I numeral 116), and a semiconductor protection layer disposed thereon (fig. 3I numeral 120); etching the semiconductor capping layer and the semiconductor protection layer to form a patterned semiconductor capping layer and a patterned semiconductor protection layer (fig. 3G – 3I show the capping layer 116 and the protection layer 120 being etched to form trenches 124; Par. [0052]; Par. [0070]); forming an interlayer dielectric layer (fig. 3I numeral 118a; fig. 5 numeral 524 shows another embodiment); forming a gate contact hole that exposed the patterned semiconductor protection layer at the bottom surface of the gate contact hole (fig. 3G numeral 128) and the gate contact hole is separated from the patterned semiconductor capping layer (fig. 3I shows the patterned protection layer 120 separating the gate contact hole filled by the gate 122 and the patterned capping layer 116); forming a gate electrode in the gate contact hole, wherein a portion of the patterned semiconductor protection layer is disposed between the gate electrode and the patterned semiconductor capping layer (fig. 3I numeral 122). Chiu does not explicitly state the resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer. However, Chiu teaches that the patterned semiconductor protection layer, the patterned semiconductor capping, and the interlayer dielectric layer may all comprise silicon dioxide or silicon nitride compounds (Par. [0060]; Par. [0051]; Par. [0065]). Silicon nitride compounds have a resistivity of approximately 1x1014 Ohm per cm and silicon dioxide compounds have a resistivity that ranges between 1x1014 and 1x1016 Ohm per cm (see table provided from EESemi). It would be obvious to one in the ordinary skill in the art before the effective filing date of the immediate invention that the embodiments in Chiu include embodiments wherein the resistivity of the patterned semiconductor protection layer is between the resistivity of the patterned semiconductor capping layer and the resistivity of the interlayer dielectric layer, based on the materials taught by Chiu and as a well-known result-effective variable in the art that one would optimize to control the electrical properties in the device including current, voltage drop off, breakdown voltage, etc. Chiu is silent regarding the interlayer dielectric layer covering the patterning semiconductor capping layer and the patterned semiconductor protection layer, and wherein the gate contact hole is formed in the interlayer dielectric layer. The interlayer dielectric layer is shown in Chiu to be patterned to allow a contact hole to be formed within the dielectric layer (fig. 3I numeral 118).
Chen teaches a HEMT device (Chen, fig. 1J – 1L) wherein a patterned semiconductor capping layer (fig. 1J numeral 152) and a patterned semiconductor protection layer (fig. 1L numeral 170) are covered by an interlayer dielectric layer (fig. 1L numeral 160), and wherein the interlayer dielectric layer is etched to form a gate contact hole (fig. 1K numeral 167; fig. 1L numeral 180).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the interlayer dielectric layer placement in Chen with the patterned semiconductor channel and protection layers in Chiu in order to protect the layers covered by the interlayer dielectric layer from external contaminates, external forces form the surrounding environment, or to better isolate the channel and protection layers from layers placed on top of the device, such as source/drain contacts, metal vias, pads, etc.
For claim 2, Chiu and Chen teach all of claim 1. Chiu also teaches before etching the semiconductor capping layer and the semiconductor protection layer, forming a mask layer on the semiconductor protection layer (Par. [0071]), and during the etching of the semiconductor capping layer and the semiconductor protection layer, removing the semiconductor capping layer and the semiconductor protection layer which are exposed from the mask layer (Par. [0071] describes forming a mask layer on the semiconductor protection layer 120, then etching the layers the art at least partially exposed as shown in the process from fig. 3H to fig. 3I, resulting in the semiconductor protection layer and capping layer being patterned).
For claim 5, Chiu and Chen teach all of claim 1. Chiu also teaches forming the gate contact hole through a photolithography and etching process (Chiu, Par. [0071]). Chen also teaches a step of forming a gate contact hole (Chen, fig. 1J – 1L) and that the process includes using photolithography and etching process (Col. 6 ln 61 – 67).
For claim 6, Chiu and Chen teach all of claim 1. Chiu and Chen are silent regarding the resistivity of the patterned semiconductor protection layer being higher than the resistivity of the gate electrode. However, Chiu teaches the patterned semiconductor protection layer comprising SiO and SiN compounds (Chiu, Par. [0060]; Par. [0051]; Par. [0065]) and the gate electrode comprising different metal and metal alloys including copper (Par. [0052]). Copper has a resistivity coefficient of approximately 1.724×10^-8 Ohm*m (see table provided from engineering toolbox) while SiO and SiN has resistivity that ranges between 1x1014 and 1x1016 Ohm per cm (see table provided from EESemi). It would be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the embodiments in Chiu and Chen include embodiments wherein the resistivity of the patterned semiconductor protection layer being higher than the resistivity of the gate electrode based on the materials taught by Chiu and Chen.
For claim 7, Chiu and Chen teach all of claim 1. Chiu also teaches the gate electrode is in direct contact with the patterned semiconductor protection layer (Chiu, fig. 3I shows the gate electrode 122 in direct contact with the patterned semiconductor protection layer 120).
For claim 8, Chiu and Chen teach all of claim 1. Chiu also teaches after forming the gate electrode, a surface of the patterned semiconductor protection layer comprises a groove (fig. 3I numeral 120), and the gate electrode fills up the groove (fig. 3I numeral 122).
For claim 9, Chiu and Chen teach all of claim 8. Chiu also teaches the patterned semiconductor protection layer has a first portion disposed on the periphery of the groove and a second portion disposed under the groove (fig. 3I numeral 120; fig. 5 numeral 520). Chiu also teaches embodiments wherein the first portion has a thickness greater than the thickness of the second portion (fig. 5 numeral W2 and W3; Par. [0088]) and that the thickness of the layers around the groove are variable (Par. [0088]; Par. [0083]; Par. [0077]).
Allowable Subject Matter
Claims 3 – 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 3, Chiu and Chen do not appear to teach that before forming the interlayer dielectric layer, the mask layer is removed, and wherein before removing the mask layer and after forming the interlayer layer dielectric layer, the width of the patterned semiconductor protection remains constant. Chiu appears to teach form the interlayer dielectric layer before the mask layer is formed (Chiu, fig. 3f shows the interlayer dielectric 118 being formed before the etching process that uses the mask is performed in fig. 3I). Chiu appears to teach the mask layer being removed after the interlayer dielectric layer is formed. Chiu appears to teach away from removing the mask layer before forming the interlayer dielectric layer.
Claim 4 is allowable primarily as depending on claim 3 but is objected to for depending on a rejected base claim.
Conclusion
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/J.T.N./Examiner, Art Unit 2815
/MONICA D HARRISON/Primary Examiner, Art Unit 2815
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