DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 are pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 9/18/2024 and 9/2/2025 are being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 12-15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 12 recites the limitation "substrate" on page 17 line 1 without being introduced. There is insufficient antecedent basis for this limitation in the claim. For compact prosecution, the examiner interprets “substrate” to mean “stacked structure”.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1, 5, 7-8, 10, 16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai (US 20230282584 A1).
Re Claim 1 Tsai teaches a 3D memory device (FIG. 1, 10) [0020], including:
a stacked structure (10), including a plurality of conductive layers (124) [0021] and a plurality of dielectric layers (122) stacked alternately (FIG. 6), wherein a top surface of the stacked structure (10) is parallel to a plane defined by a first direction (DIII in FIG. 1) and a second direction (DII);
a first group of channel structures (VC1 [0021] in BK11 and BK12 in FIG. 1) and a second group of channel structures (VC1 [0021] in BK13 and BK14 in FIG. 1), penetrating the stacked structure (10) and arranged along the first direction (DIII);
a first partition structure (LT2) [0023], including a plurality of discrete partition structures (LT2 in HP1 and HP2 in FIG. 1) disposed between the first group of channel structures (VC1 [0021] in BK11 and BK12 in FIG. 1) and the second group of channel structures (VC1 [0021] in BK13 and BK14 in FIG. 1), wherein the plurality of discrete partition structures (LT2 in HP1 and HP2) are arranged along the second direction (DII) and penetrate the stacked structure (10); and
at least one support structure (OW) [0026], disposed between the adjacent discrete partition structures (LT2 in HP1 and HP2, FIG. 2 and 9).
Re Claim 5 Tsai teaches the 3D memory device according to claim 1, wherein the number of the at least one supporting structure (OW) is two or more (FIG. 2 shows 2 OW structures between LT2 from DIII view).
Re Claim 7 Tsai teaches the 3D memory device according to claim 1 further comprising:
a second partition structure (LT1) [0023], disposed at a first side (lower end of BK11 in FIG. 1) of the first group of channel structures (VC1 in BK11 and BK12 in FIG. 1) and extending continuously along the second direction (DII), and the first partition structure (LT2) disposed at a second side (between BK12 and BK13 in FIG. 1) of the first group of channel structures (VC1 in BK11 and BK12 in FIG. 1).
Re Claim 8 Tsai teaches the 3D memory device according to claim 7, wherein a length of the second partition structure (LT1) is greater than a sum of lengths of the plurality of discrete partition structures (LT2 in HP1 and HP2) of the first partition structure (FIG. 1).
Re Claim 10 Tsai teaches the 3D memory device according to claim 1, wherein a material (dielectric) [0042] of the at least one support structure (OW) is different from a material (tungsten) [0023] of a source plane contact (inner part of LT2, [0023] states, “Each trench (LT1 to LT5) has a side surface (or wall) covered with a dielectric film (e.g., oxide) isolated from adjacent layers (e.g., conductive layers 124) and an inner part filled with a conductive material (e.g., tungsten).”) of one of the plurality of the discrete partition structures (LT1, FIG. 1).
Re Claim 16 Tsai teaches the 3D memory device according to claim 1, further including:
a third partition structure (LT4) [0023], including a plurality of discrete partition structures (LT4 in HP1 and HP2) disposed at a side (above in DIII direction) of the second group of channel structures (VC1 in BK13 and BK14 in FIG. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2-4, 6, 9, 12-14, 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230282584 A1) in view of Kim et al. (US 20240224514 A1).
Re Claim 2 Tsai teaches the 3D memory device according to claim 1, but does not teach a distance between one of the at least one support structure and a closest channel structure in one of the first group of channel structures and the second group of channel structures is 20 nm to 400 nm.
Kim teaches [0081] “…D4 may be equal to or greater than the second horizontal diameter D2…”, [0060] “…D2 may be equal to or greater than the first horizontal diameter D1 and may range from tens of nm to hundreds of nm.”, and D1 is the diameter of the channel holes [0060]. Using 20 nm for D4 from FIG. 18B leads to 360’s diameter being about 20 nm and the distance separating support structure (360D, [0086] “…360D may be referred to as a support structure.”) and the closest channel structure (360) [0086] is between 20 nm and 100 nm apart making a distance between one of the at least one support structure (360D) and a closest channel structure (360) in one of the first group of channel structures (MCR on left in FIG. 29B) and the second group of channel structures is in the range of 20 nm to 400 nm.
Modified FIG. 29B shown below
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It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai since Kim teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in the above manner for the motivation of finding the optimal distance between the closest channel structure and the at least one support structure to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between a channel structure and the closest support structure.
Re Claim 3 Tsai teaches the 3D memory device according to claim 1, but does not teach a distance between one of the at least one support structure and a closest channel structure in one of the first group of channel structures and the second group of channel structures is 20 nm to 100 nm.
Kim teaches [0081] “…D4 may be equal to or greater than the second horizontal diameter D2…”, [0060] “…D2 may be equal to or greater than the first horizontal diameter D1 and may range from tens of nm to hundreds of nm.”, and D1 is the diameter of the channel holes [0060]. Using 20 nm for D4 from FIG. 18B leads to 360’s diameter being about 20 nm leads to the distance separating support structure (360D, [0086] “…360D may be referred to as a support structure.”) and the closest channel structure (360) [0086] is between 20 nm and 100 nm apart making a distance between one of the at least one support structure (360D) and a closest channel structure (360) in one of the first group of channel structures (360 in MCR on left in FIG. 29B) and the second group of channel structures is in the range of 20 nm to 100 nm (see modified Kim FIG. 29B under claim 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai since Kim teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in the above manner for the motivation of finding the optimal distance between the closest channel structure and the at least one support structure to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between a channel structure and the closest support structure.
Re Claim 4 Tsai teaches the 3D memory device according to claim 1, but does not explicitly teach a distance between one of the at least one support structure and a closest one of the plurality of discrete partition structures is 20 nm to 400 nm.
Kim teaches [0081] “…D4 may be equal to or greater than the second horizontal diameter D2…”, [0060] “…D2 may be equal to or greater than the first horizontal diameter D1 and may range from tens of nm to hundreds of nm.”, and D1 is the diameter of the channel holes [0060]. Using 20 nm for D4 from FIG. 18B leads to 360’s diameter being about 20 nm. Tsai FIG. 1 shows discrete partition structures (LT2) and OW are spaced apart by about 2x to 3x the diameter of a channel (VC1). Integrating 20 nm for a channel diameter from Kim into Tsai FIG. 1 leads to Tsia LT2 and OW being about 40 nm to 60 nm apart.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai since Kim teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in the above manner for the motivation of finding the optimal distance between the discrete partition structures and one of the at least one support structure to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between a channel structure and the closest support structure.
Re Claim 6 Tsai teaches the 3D memory device according to claim 5, but does not teach a distance between the adjacent supporting structures is less than or equal to 400nm.
Kim modified FIG. 29B under claim 2 shows a distance between the first support structure (top 360D) and the closest channel structure (360) to be up to 100 nm apart from each other. Kim modified FIG. 29B further shows the distance between the first support structure (top 360D) and a second support structure (bottom, 360D) is about double the distance between supporting structure (360D) and the closest channel structure (360). Therefore, a distance between the adjacent supporting structures (360D structures in modified FIG. 29 under claim 2) is less than or equal to 400nm.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai since Kim teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in the above manner for the motivation of finding the optimal distance between the support structures to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between the support structures.
Re Claim 9 Tsai in view of Kim teaches the 3D memory device according to claim 1, wherein a material (silicon oxide) [0088] of the at least one support structure (Kim, 360D) is the same as a material (silicon oxide) [0119] of an insulating pillar (362A) of one channel structure (360) among the first group of channel structures (360 in MCR on left in FIG. 29B) and the second group (360 in MCR on right in FIG. 29B) of channel structures (360, FIG. 28C and 29B).
Re Claim 12 Tsai in view of Kim teaches the 3D memory device according to claim 1, wherein the substrate (stacked structure, Tsai, 10) includes an array region (HP1) [0021] and a step region (CR, [0024] “connection region”), and the first group of channel structures (VC1 in BK11 and BK12 in FIG. 1) and the second group of channel structures (VC1 in BK13 and BK14 in FIG. 1) are disposed in the array region (HP1, FIG. 1).
Re Claim 13 Tsai in view of Kim teaches the 3D memory device according to claim 12, further including at least one dummy support structure (Kim, top 360D) disposed in the step region (CONR, [0041] “connection area”, FIG. 29B).
Re Claim 14 Tsai in view of Kim teaches the 3D memory device according to claim 13, wherein the at least one dummy support structure (Kim, 360D) includes a plurality of dummy support structures (360D) arranged in an array pattern (vertical line, FIG. 29B).
Re Claim 17 Tsai teaches a 3D memory device (FIG. 1, 10) [0020], including:
a first structure (120), including a source line plane (FIG. 4) [0021]; and
a second stacked structure (122 & 124) [0022], disposed over the first structure (120) and including a plurality of conductive layers (124) and a plurality of dielectric layers (122) stacked alternately (FIG. 4);
a first group of channel structures (VC1 [0021] in BK11 and BK12 in FIG. 1) and a second group of channel structures (VC1 [0021] in BK13 and BK14 in FIG. 1), penetrating the second stacked structure (122 & 124) and arranged along a first direction (DIII shown in FIG. 1);
a separation structure (LT1-5) [0023], including:
a first partition structure (LT2), including a plurality of discrete partition structures (LT2 in HP1 and HP2 in FIG. 1) disposed between the first group of channel structures (VC1 [0021] in BK11 and BK12 in FIG. 1) and the second group of channel structures (VC1 [0021] in BK13 and BK14 in FIG. 1), wherein the plurality of discrete partition structures are arranged along a second direction (DII) different from the first direction (DIII) and penetrate the second stacked structure (122 & 124, FIG. 10); and
a second partition structure (LT3), extending continuously along the second direction (DII) and penetrating the second stacked structure (122 & 124), wherein the second partition structure (LT3) and the first partition structure (LT2) are parallel along the first direction (DIII); and
at least one support structure (OW) [0026], disposed between the adjacent discrete partition structures (LT2 in HP1 and HP2 in FIG. 1).
Tsai does not teach the first structure is a stacked structure.
Kim teaches the first structure (PS) [0033] is a stacked structure (FIG. 10A).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai since Kim teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in the above manner for the motivation of having the first structure be a stacked structure to allow one to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…”
Re Claim 18 Tsai in view of Kim teaches the 3D memory device according to claim 1, wherein a material (Kim, silicon oxide) [0088] of the at least one support structure (360D) [0086] is the same as a material (silicon oxide) [0119] of an insulating pillar (362A) of one channel structure (360) [0086] among the first group of channel structures (360 in MCR on left in FIG. 29B) and the second group (360 in MCR on right in FIG. 29B) of channel structures (360, FIG. 28C and 29B).
Re Claim 19 Tsai in view of Kim teaches the 3D memory device according to claim 17, but does not explicitly teach a distance between one of the at least one support structure and a closest channel structure in one of the first group of channel structures and the second group of channel structures is 20 nm to 400 nm.
Kim teaches [0081] “…D4 may be equal to or greater than the second horizontal diameter D2…”, [0060] “…D2 may be equal to or greater than the first horizontal diameter D1 and may range from tens of nm to hundreds of nm.”, and D1 is the diameter of the channel holes [0060]. Using 20 nm for D4 from FIG. 18B leads to 360’s diameter being about 20 nm and the distance separating support structure (360D, [0086] “…360D may be referred to as a support structure.”) and the closest channel structure (360) [0086] is between 20 nm and 100 nm apart making a distance between one of the at least one support structure (360D) and a closest channel structure (360) in one of the first group of channel structures (MCR on left in FIG. 29B) and the second group of channel structures is in the range of 20 nm to 400 nm (see Kim modified FIG. 29B under claim 2).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai in view of Kim.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in view of Kim in the above manner for the motivation of finding the optimal distance between the closest channel structure and the at least one support structure to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between a channel structure and the closest support structure.
Re Claim 20 Tsai in view of Kim teaches the 3D memory device according to claim 17, but does not explicitly teach a distance between one of the at least one support structure and a closest one of the plurality of discrete partition structures is 20 nm to 400 nm.
Kim teaches [0081] “…D4 may be equal to or greater than the second horizontal diameter D2…”, [0060] “…D2 may be equal to or greater than the first horizontal diameter D1 and may range from tens of nm to hundreds of nm.”, and D1 is the diameter of the channel holes [0060]. Using 20 nm for D4 from FIG. 18B leads to 360’s diameter being about 20 nm. Tsai FIG. 1 shows discrete partition structures (LT2) and OW are spaced apart by about 2x to 3x the diameter of a channel (VC1). Integrating 20 nm for a channel diameter from Kim into Tsai FIG. 1 leads to Tsia LT2 and OW being about 40 nm to 60 nm apart.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Kim into the structure of Tsai in view of Kim.
The ordinary artisan would have been motivated to modify Kim in combination with Tsai in view of Kim in the above manner for the motivation of finding the optimal distance between the discrete partition structures and one of the at least one support structure to build a nonvolatile memory device. [0002] states, “Various example embodiments relate to an integrated circuit device and/or an electronic system including the integrated circuit device, and more particularly, to an integrated circuit device including a nonvolatile memory device…” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal distance between a channel structure and the closest support structure.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230282584 A1).
Re Claim 11 Tsai teaches the 3D memory device according to claim 1, but does not explicitly teach a ratio of a width or diameter of the at least one support structure to a width or diameter of the channel structure is in a range from 1 to 3.
Tsai FIG. 1 shows the width of a cross section of support structure (OW) level with LT2 in DIII direction is close to the diameter of channel structure (VC1) concluding the ratio of the width of the at least one support structure to a diameter of the channel structure is about 1.
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Tsai into the structure of Tsai.
The ordinary artisan would have been motivated to modify Tsai in combination with Tsai in the above manner for the motivation of finding the optimal ratio of the width of the at least one support structure to a diameter of the channel structure to build a 3D memory device with a maximum storage capacity. [0002] states, “With more and more applications nowadays, how to provide memory devices with higher storage capacity has become one of important ways for study.” Furthermore, it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233. In the instant case, process optimization will allow one of ordinary skill in the art to reach the optimal ratio of the width of the at least one support structure to a diameter of the channel structure.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Tsai (US 20230282584 A1) in view of Kim et al. (US 20240224514 A1) as applied to claims 12 and 13 above, and further in view of Jung et al. (CN 118632529 A).
Re Claim 15 Tsai in view of Kim teaches the 3D memory device according to claim 13, wherein a material of the at least one dummy support structure (Kim, 360D, FIG. 29B) is silicon oxide [0088].
Tsai in view of Kim does not teach a material of the at least one dummy support structure is the same as a material of the at least one support structure.
Jung teaches the support structure (210, page 14 par 4, FIG. 6D) comprises silicon oxide, and integrating Jung into Tsai in view of Kim will teach a material (silicon oxide) of the at least one dummy support structure (Kim, 360D, FIG. 29B) is the same as a material (silicon oxide) of the at least one support structure (Jung, 210, FIG. 6D).
It would have been obvious to one ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching as taught by Jung into the structure of Tsai in view of Kim since Jung teaches a NAND 3D memory device.
The ordinary artisan would have been motivated to modify Jung in combination with Tsai in view of Kim in the above manner for the motivation of forming the at least one dummy support structure to contain a same material as the at least one support structure to build a 3D NAND structure capable so stored data is reserved even if the power supply is interrupted. Page 2 par 2 states, “The memory device may be classified as a volatile memory device where the stored data disappears when the power supply is interrupted and a non-volatile memory device where the stored data is reserved even if the power supply is interrupted.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Sai et al. (US 20240121959 A1) teaches a 3D NAND memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KENNETH MARK SIPLING whose telephone number is (571)272-3269. The examiner can normally be reached 10 AM - 6 PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KENNETH MARK SIPLING/ Examiner, Art Unit 2818
/DUY T NGUYEN/ Primary Examiner, Art Unit 2818 9/15/26
Prosecution Insights