DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in Korean Patent Application No. 10-2021-0145733, filed on 10/28/2021.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statements (IDSs) submitted on 9/18/2024, 11/15/2024, 3/26/2025, and 3/28/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 1 and 4 are objected, because the following limitations/phrases should be aligned to the prior limitations/phrases to avoid 112 issues due to indefiniteness:
Regarding claim 1, on the last line, “the first conductive pattern contact” does not have an antecedent basis. This should be due to a typo. For the purpose of examination, the Examiner considered “the first conductive pattern contact” to be “the first conductive pattern ”.
Regarding claim 4, on line 2, “a width, in the first direction, of each of the plurality of first vias” should be rephrased as “the width, in the first direction, of each of the plurality of first vias”, as “the width, in the first direction, of each of the plurality of first vias” was already introduced in claim 3, on which claim 4 depends.
Appropriate corrections are required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-5 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-6 of U.S. Patent No. US 12,199,016 B2 (will be referred as Ding-016), respectively.
Instant Application- 18/888,158
US Pat. No. US 12,199,016 B2 (Ding-016)
Claim 1:
A semiconductor device, comprising:
a substrate that includes a first region and a second region;
an integrated circuit provided at the first region of the substrate;
an interlayer dielectric layer on the substrate;
a contact on the first region, the contact penetrating the interlayer dielectric layer to be connected to the integrated circuit;
a through electrode at the second region, the through electrode penetrating the substrate and the interlayer dielectric layer;
a capping layer on the substrate, the capping layer covering the integrated circuit and the contact;
an intermetal dielectric layer on the capping layer;
a first conductive pattern in the intermetal dielectric layer, wherein the first conductive pattern is disposed on the second region; and
a plurality of first vias penetrating the intermetal dielectric layer and the capping layer and connecting the through electrode to the first conductive pattern,
the plurality of first vias being arranged in a plurality of rows extending in a first direction and a plurality of columns extending in a second direction,
wherein the first and second directions intersect each other and are parallel to a top surface of the substrate,
wherein each of the plurality of first vias has a bar shape that extends in the first direction,
wherein each row of the plurality of first vias is formed of at least two first vias arranged in the first direction,
wherein a sum of a width, in the first direction, of each of the at least two first vias in each row of the plurality of first vias is equal to or less than a width, in the first direction, of a corresponding portion of the first conductive pattern, and
wherein the at least two first vias contact the corresponding portion of the first conductive pattern see claim objections above).
Claim 1:
A semiconductor device, comprising:
a substrate that includes a first region and a second region;
an integrated circuit provided at the first region of the substrate;
an interlayer dielectric layer on the substrate;
a contact on the first region, the contact penetrating the interlayer dielectric layer to be connected to the integrated circuit;
a through electrode at the second region, the through electrode penetrating the substrate and the interlayer dielectric layer;
a capping layer on the substrate, the capping layer covering the integrated circuit and the contact;
a first intermetal dielectric layer on the capping layer;
a first conductive pattern in the first intermetal dielectric layer, wherein the first conductive pattern is disposed on the second region; and
a plurality of first vias penetrating the first intermetal dielectric layer and the capping layer and connecting the through electrode to the first conductive pattern,
the plurality of first vias being arranged in a plurality of rows extending in a first direction and a plurality of columns extending in a second direction,
wherein the first and second directions intersect each other and are parallel to a top surface of the substrate,
wherein each of the plurality of first vias has a bar shape that extends in the first direction,
wherein each row of the plurality of first vias is formed of at least two first vias arranged in the first direction,
wherein a sum of a width, in the first direction, of each of the at least two first vias in each row of the plurality of first vias is equal to or less than a width, in the first direction, of a corresponding portion of the first conductive pattern,
wherein the at least two first vias contact the corresponding portion of the first conductive pattern,
and wherein the plurality of first vias are interposed between the first conductive pattern and the through electrode.
Claim 2:
The semiconductor device of claim 1, further comprising:
a second conductive pattern in the intermetal dielectric layer on the first region;
a second via penetrating the intermetal dielectric layer and the capping layer and connecting the contact to the second conductive pattern,
wherein a width, in the first direction, of each of the plurality of first vias is greater than a width, in the first direction, of the second via.
Claim 2:
The semiconductor device of claim 1, further comprising:
a second conductive pattern in the first intermetal dielectric layer on the first region; and
a second via penetrating the first intermetal dielectric layer and the capping layer and connecting the contact to the second conductive pattern,
wherein a width, in the first direction, of each of the plurality of first vias is greater than a width, in the first direction, of the second via.
Claim 3:
The semiconductor device of claim 2,
wherein the width, in the first direction, of each of the plurality of first vias is about 2 times to about 50 times the width, in the first direction, of the second via.
Claim 3:
The semiconductor device of claim 2,
wherein the width, in the first direction, of each of the plurality of first vias is about 2 times to about 50 times the width, in the first direction, of the second via.
Claim 4:
The semiconductor device of claim 3,
wherein a width, in the first direction, of each of the plurality of first vias is about 2 times to about 100 times a width, in the second direction, of each of the plurality of first vias.
Claim 5:
The semiconductor device of claim 3,
wherein ones of the first vias are connected to each other in the first direction, the ones of the first vias constituting a single row in the first direction.
Claim 4:
The semiconductor device of claim 1,
wherein a width, in the first direction, of each of the plurality of first vias is greater than a width, in the second direction, of each of the plurality of first vias.
Claim 5:
The semiconductor device of claim 4,
wherein the width, in the first direction, of each of the plurality of first vias is about 2 times to about 100 times the width, in the second direction, of each of the plurality of first vias.
Claim 6:
The semiconductor device of claim 1,
wherein ones of the first vias are connected to each other in the first direction, the ones of the first vias constituting a single row in the first direction.
Regarding claim 1, Ding-016’s claim 1 recites all the limitations of claim 1 (“intermetal layer” of the current application corresponds to “first intermetal dielectric layer” of Ding-016).
Regarding claim 2, Ding-016’s claim 1 teaches claim 1, and Ding-016’s claim 2 recites all the limitations of claim 2.
Regarding claim 3, Ding-016’s claim 2 teaches claim 2, and Ding-016’s claim 3 recites all the limitations of claim 3.
Regarding claim 4, Ding-016’s claim 3 teaches claim 3, and Ding-016’s claim 5 recites all the limitations of claim 4.
Regarding claim 5, the scope of Ding-016’s claim 1-6 covers all limitations of claim 5.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-4 are rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0256476 A1) in view of Wong-Embodiment 1-Embodiment 1 (US 2013/0277854 A1, the embodiment shown in Figs. 5 and 7).
Regarding claim 1, Kim teaches a semiconductor device (semiconductor device 1, Fig. 1L, [0034]), comprising:
a substrate (substrate 100, Fig. 1L, [0033]) that includes a first region (see first region as illustrated in Illustrative Fig. 1, which is an annotated version of Kim’s Fig. 1L) and a second region (second region, Illustrative Fig. 1);
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an integrated circuit (integrated circuit 102, Illustrative Fig. 1, [0018]) provided at the first region of the substrate (first region, Illustrative Fig. 1);
an interlayer dielectric layer (interlayer dielectric layer 110, Illustrative Fig. 1, [0019]) on the substrate (substrate 100, Illustrative Fig. 1);
a contact (electrical contacts 104 and first metal lines 151, Illustrative Fig. 1, [0025]) on the first region (first region, Illustrative Fig. 1), the contact penetrating the interlayer dielectric layer (interlayer dielectric layer 110, Illustrative Fig. 1) to be connected to the integrated circuit (integrated circuit 102, Illustrative Fig. 1, [0018]: “The electrical contacts 104 may be in contact with the substrate 100 and electrically connected to the substrate 100 and/or the integrated circuit 102.”);
a through electrode (through electrode 140, Illustrative Fig. 1) at the second region (first region, Illustrative Fig. 1), the through electrode (through electrode 140, Illustrative Fig. 1) penetrating the substrate (substrate 100, Illustrative Fig. 1) and the interlayer dielectric layer (interlayer dielectric layer 110, Illustrative Fig. 1);
a capping layer (first capping layer 123, Illustrative Fig. 1, [0026]) on the substrate (substrate 100, Illustrative Fig. 1), the capping layer (first capping layer 123, Illustrative Fig. 1) covering the integrated circuit (integrated circuit 102, Illustrative Fig. 1) and the contact (electrical contacts 104 and first metal lines 151, Illustrative Fig. 1);
an intermetal dielectric layer (first intermetal dielectric layer 161, Illustrative Fig. 1, [0026]) on the capping layer (first capping layer 123, Illustrative Fig. 1);
a first conductive pattern (the top portions of second metal lines 154 when they are formed by a dual damascene process and have the same shapes as the second metal lines 153 (see [0028]), Illustrative Fig. 1, [0028]) in the intermetal dielectric layer (first intermetal dielectric layer 161, Illustrative Fig. 1), wherein the first conductive pattern (top portions of second metal lines 154, Illustrative Fig. 1) is disposed on the second region (second region, Illustrative Fig. 1); and
a plurality of first vias (bottom portions of second metal lines 154 when they are formed by a dual damascene process and have the same shapes as the second metal lines 153 (see [0028]), Illustrative Fig. 1) penetrating the intermetal dielectric layer (first intermetal dielectric layer 161, Illustrative Fig. 1) and the capping layer (first capping layer 123, Illustrative Fig. 1) and connecting the through electrode (through electrode 140, Illustrative Fig. 1) to the first conductive pattern (top portions of second metal lines 154, Illustrative Fig. 1).
Kim, however, is silent on the two-dimensional plan view arrangement of the first vias, and therefore is silent on that
the plurality of first vias being arranged in a plurality of rows extending in a first direction and a plurality of columns extending in a second direction,
wherein the first and second directions intersect each other and are parallel to a top surface of the substrate,
wherein each of the plurality of first vias has a bar shape that extends in the first direction,
wherein each row of the plurality of first vias is formed of at least two first vias arranged in the first direction,
wherein a sum of a width, in the first direction, of each of the at least two first vias in each row of the plurality of first vias is equal to or less than a width, in the first direction, of a corresponding portion of the first conductive pattern, and
wherein the at least two first vias contact the corresponding portion of the first conductive pattern(see claim objections).
Wong-Embodiment 1, on the other hand, teaches an analogous semiconductor device (integrated circuit system 100, Fig. 5, [0015]) comprising a through electrode (TSV 200, Fig. 5, [0027]), an integrated circuit (comprising MOSFETs in Fig. 5, [0014]), an overlying conductive layer (conductive layer 500, Fig. 5, [0032]), and an insulating layer (insulation layer 300, Fig. 5, [0033]). Wong-Embodiment 1 further teaches that the through electrode (TSV 200, Fig. 5) and the conductive layer (conductive layer 500, Fig. 5) are connected though a via structure (via structure 710, Fig. 7, [0035]) analogous to plurality of first vias of Kim, wherein
the plurality of first vias (bar-line patterns 710a, Fig. 7, [0035]) being arranged in a plurality of rows (see rows in illustrative Fig. 2, which is an annotated version of Wong-Embodiment 1’s Fig. 7) extending in a first direction (first direction, illustrative Fig. 2) and a plurality of columns (columns, Illustrative Fig. 2) extending in a second direction (second direction, illustrative Fig. 2),
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wherein the first (first direction, illustrative Fig. 2) and second (second direction, illustrative Fig. 2) directions intersect each other and are parallel to a top surface of the substrate (substrate 102, see Fig. 1 for the label, [0015]),
wherein each of the plurality of first vias (bar-line patterns 710a, Illustrative Fig. 2) has a bar shape ([0035]: “bar-line patterns 710a”) that extends in the first direction (first direction, illustrative Fig. 2),
wherein each row (rows, Illustrative Fig. 2) of the plurality of first vias is formed of at least two first vias (bar-line patterns 710a, Illustrative Fig. 2) arranged in the first direction (first direction, illustrative Fig. 2),
wherein a sum of a width (sum of width W1 and width W2, Illustrative Fig. 2), in the first direction (first direction, illustrative Fig. 2), of each of the at least two first vias (bar-line patterns 710a, illustrative Fig. 2) in each row (rows, Illustrative Fig. 2) of the plurality of first vias (bar-line patterns 710a, illustrative Fig. 2) is equal to or less than a width (width W3, Illustrative Fig. 2), in the first direction (first direction, illustrative Fig. 2), of a corresponding portion of the first conductive pattern (because the vias are for making contact between the conductive layer 500 and TSV 200 (Fig. 5), the region between the two first vias corresponds to the conductive pattern, therefore W1 + W2 < W3), and
wherein the at least two first vias (bar-line patterns 710a, Illustrative Fig. 2) contact the corresponding portion of the first conductive pattern (conductive layer 500, Fig. 5)(see claim objections).
Wong-Embodiment 1 further discloses that “the via bar net pattern 710a and 710b serves to increase the contact area between the TSV and M1, and decreases stress-induced via voids” ([0036]). Therefore, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the first vias in the semiconductor device of Kim according to the teachings of Wong-Embodiment 1 to obtain the benefit of increasing the contact area while decreasing the stress induced via voids. Thus, the combination of Kim and Wong-Embodiment 1 meets all the limitations of claim 1.
Regarding claim 2, Kim in view of Wong-Embodiment 1 teaches the semiconductor device of claim 1,
wherein KIm also teaches that the semiconductor device further comprises:
a second conductive pattern (second metal line 153, Illustrative Fig. 1, [0027]) in the intermetal dielectric layer (first intermetal dielectric layer 161, Illustrative Fig. 1) on the first region (first region, Illustrative Fig. 1);
a second via (via below the second metal line 153, Illustrative Fig. 1) penetrating the intermetal dielectric layer (first intermetal dielectric layer 161, Illustrative Fig. 1) and the capping layer (first capping layer 123, Illustrative Fig. 1) and connecting the contact (electrical contacts 104 and first metal lines 151, Illustrative Fig. 1) to the second conductive pattern (second metal line 153, Illustrative Fig. 1).
Kim is, however, silent on the width of the first and second vias, and therefore does not teach that
a width, in the first direction, of each of the plurality of first vias is greater than a width, in the first direction, of the second via.
Wong-Embodiment 1, on the other hand, teaches that
a width (width W1, Illustrative Fig. 2), in the first direction (first direction, Illustrative Fig. 2), of each of the plurality of first vias (bar-line patterns 710a, Illustrative Fig.2) is greater than a width, in the first direction (first direction, Illustrative Fig. 2), of the second via (other vias in the device, [0036]: “via structure 700 is formed using the minimum via width allowed according to the particular design constraints of the IC design, although greater via widths can be used if desired. The via bar net pattern 710a and 710b serves to increase the contact area between the TSV and M1, and decreases stress-induced via voids.”, where the width in [0036] refers to width in the second direction).
Accordingly, because the width of the first vias in the first direction is larger than the width of the first vias in the first direction (Illustrative Fig 2), a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to form the second vias in the semiconductor device of Kim in view of Wong-Embodiment 1 with minimum allowable width to obtain a minimum device size. Therefore, the combination of Kim in view of Wong-Embodiment 1 would lead to a device where a width, in the first direction, of each of the plurality of first vias is greater than a width, in the first direction, of the second via.
Regarding claim 3, while Kim in view of Wong-Embodiment 1 teaches the semiconductor device of claim 2,
neither Kim nor Wong-Embodiment 1 discloses that
the width, in the first direction, of each of the plurality of first vias is about 2 times to about 50 times the width, in the first direction, of the second via.
Wong-Embodiment 1, however, discloses that “the via bar net pattern 710a and 710b serves to increase the contact area between the TSV and M1, and decreases stress-induced via voids” ([0036]) and “via structure 700 is formed using the minimum via width allowed according to the particular design constraints of the IC design” ([0036]), where the width referred by Wong-Embodiment 1 is in the second direction. Therefore, increase in the contact area is accomplished by elongating the first vias in the first direction. Accordingly, the width of the first vias in the first direction is a result-effective variable, and it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the first vias in the first direction to obtain a desired device performance (see MPEP 2144.05). Accordingly, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed widths such that, in the first direction, of each of the plurality of first vias is about 2 times to about 50 times the width, in the first direction, of the second via (see MPEP 2144.05) in order to achieve a desired device performance.
Regarding claim 4, while Kim in view of Wong-Embodiment 1 teaches the semiconductor device of claim 3,
neither Kim nor Wong-Embodiment 1 discloses that
wherein a width, in the first direction, of each of the plurality of first vias is about 2 times to about 100 times a width, in the second direction, of each of the plurality of first vias.
Wong-Embodiment 1, however, discloses that “the via bar net pattern 710a and 710b serves to increase the contact area between the TSV and M1, and decreases stress-induced via voids” ([0036]) and “via structure 700 is formed using the minimum via width allowed according to the particular design constraints of the IC design” ([0036]), where the width referred by Wong-Embodiment 1 is in the second direction. Therefore, increase in the contact area is accomplished by elongating the first vias in the first direction. Accordingly, the width of the first vias in the first direction is a result-effective variable, and it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to vary, through routine optimization, the width of the first vias in the first direction to obtain a desired device performance (see MPEP 2144.05). Accordingly, a person of ordinary skill in the art would have had a reasonable expectation of success to arrive at the claimed widths such that, in the first direction, of each of the plurality of first vias is about 2 times to about 100 times the width, in the second direction, of each of the plurality of first vias (see MPEP 2144.05) in order to achieve a desired device performance.
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Kim (US 2017/0256476 A1) in view of Wong-Embodiment 1 (US 2013/0277854 A1, the embodiment shown in Figs. 5 and 7) as applied to claims 1-4 above, and further in view of Wong-Embodiment 2 (US 2013/0277854 A1, the embodiment shown in Figs. 5 and 6).
Regarding claim 5, while Kim in view of Wong Embodiment 1 teaches the semiconductor device of claim 3,
Kim and Wong Embodiment 1 do not teach that
ones of the first vias are connected to each other in the first direction, the ones of the first vias constituting a single row in the first direction.
Wong-Embodiment 2, on the other hand, teaches a plurality of first vias (via structure 600, Fig. 6, [0033]) wherein
ones of the first vias (the horizontal lines of the "bar net" pattern 610, Fig. 6, [0033]) are connected to each other in the first direction (horizontal direction in Fig. 6), the ones of the first vias (the horizontal lines of the "bar net" pattern 610, Fig. 6) constituting a single row (each horizontal line in Fig. 6) in the first direction (horizontal direction in Fig. 6).
Wong-Embodiment 1 discloses that “the via bar net pattern 710a and 710b serves to increase the contact area between the TSV and M1, and decreases stress-induced via voids” ([0036]) and “via structure 700 is formed using the minimum via width allowed according to the particular design constraints of the IC design” ([0036]), where the width referred by Wong-Embodiment 1 is in the second direction. Therefore, for maximizing the contact area, a person of ordinary skill in the art before the effective filing date of the claimed invention would be motivated to elongate each one of the plurality of first vias further in the first direction such that ones of the first vias are connected to each other to form a single row, as taught by Wong-Embodiment 2. Thus, the combination of Kim, Wong-Embodiment 1, and Wong-Embodiment-2 meets all the limitations of claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jin (US 2015/0287680 A1) teaches a semiconductor device with a through electrode, an integrated circuit, and first and second vias, which is relevant to all claims.
Park (US 2015/0102497 A1) teaches a semiconductor device with a through electrode, an integrated circuit, and first and second vias, which is relevant to all claims.
Ramachandran (US 9,219,032 B2) teaches a semiconductor device with a through electrode, an integrated circuit, and first and second vias, which is relevant to all claims.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ILKER OZDEN whose telephone number is (703)756-5775. The examiner can normally be reached Monday - Friday 8:30am-5:30pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ILKER NMN OZDEN/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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