DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the following communications: the Application filed September 18, 2024.
Claims 1-18 are pending. Claim 1 is independent.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55 received on December 4, 2025.
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on September 18, 2024. This IDS has been considered.
Drawings
Figures 1-4 should be designated by a legend such as --Prior Art-- because only that which is old is illustrated. See MPEP § 608.02(g).
Applicant’s Figures 1-4 are identical to U.S. 2021/0241837 Figures 1-4.
Corrected drawings in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. The replacement sheet(s) should be labeled “Replacement Sheet” in the page header (as per 37 CFR 1.84(c)) so as not to obstruct any portion of the drawing figures. If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-9 and 15-16 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Date (U.S. 2021/0241837).
PNG
media_image1.png
792
708
media_image1.png
Greyscale
Regarding independent claim 1, Date discloses a semiconductor memory device (Figs. 1-25) comprising:
a substrate (Fig. 8: 100) that includes a first region and a second region arranged in a first direction (see Examiner’s Markup Date’s Figure 8), a third region disposed between the first region and the second region (see Examiner’s Markup Date’s Figure 8), and a fourth region disposed between the first region and the third region (see Examiner’s Markup Date’s Figure 8);
a plurality of memory blocks extending in the first direction across the first region, the fourth region, and the third region, the plurality of memory blocks being arranged in a second direction intersecting with the first direction (Fig. 8: BLKs);
a first wiring layer including a plurality of wirings extending in the second direction and arranged in the first direction in the first region, the fourth region, and the third region (Fig. 24: D0 including d0s); and
a second wiring layer (Fig. 9: M2), the plurality of memory block (Fig. 8: BLKs) being disposed between the first wiring layer (Fig. 24: D0) and the second wiring layer (Fig. 9: M2),
the plurality of memory blocks (Fig. 8: BLKs) comprising:
a plurality of word lines (Fig. 9: 110) extending in the first direction across the first region, the fourth region, the third region, and the fourth region, the plurality of word lines being arranged in a third direction intersecting with the first direction and the second direction (see page 7, par. 0116);
a first select gate line that is disposed in the first region and farther from the substrate than the plurality of word lines (Figs. 9 and 12: first 110 (SGD) farther from the substrate 100 than the word lines WL);
a second select gate line that is disposed in the first region and closer to the substrate than the plurality of word lines (Figs. 9 and 12: second 110 (SGD) farther from the substrate 100 than the word lines WL);
a first semiconductor layer disposed in the first region, the first semiconductor layer extending in the third direction and being opposed to the plurality of word lines, the first select gate line, and the second select gate line (Fig. 9: 120s);
a third select gate line that is disposed in the second region and farther from the substrate than the plurality of word lines (Figs. 9 and 12: third 110 (SGD) farther from the substrate 100 than the word lines WL);
a fourth select gate line that is disposed in the second region and closer to the substrate than the plurality of word lines (Figs. 9 and 12: 111 (SGSb) closer from the substrate 100 than the word lines WL);
a second semiconductor layer disposed in the second region, the second semiconductor layer extending in the third direction and being opposed to the plurality of second word lines, the third select gate line, and the fourth select gate line (Fig. 9: 120s);
a first contact electrode disposed in one of the third region and the fourth region, the first contact electrode extending in the third direction and being connected to one of the plurality of word lines (Fig. 10A: CCs); and
a second contact electrode disposed in the other of the third region and the fourth region, the second contact electrode extending in the third direction and being connected to one of the plurality of wirings in the first wiring layer and a wiring in the second wiring layer (Fig. 10A: CCs are electrically connected to the plurality of wirings), and
the plurality of wirings in the wiring layer includes:
a first bit line extending in a third direction, the first bit line being disposed at a position overlapping with the first semiconductor layer viewed in the third direction (Fig. 9: BLs); and
a second bit line extending in the third direction, the second bit line being disposed at a position overlapping with the second semiconductor layer viewed in the third direction (Fig. 9: BLs; and
a plurality of first wirings disposed at a position over lapping with the first contact electrode and the second contact electrode viewed in the third direction (Fig. 9: m0s).
Regarding claim 2, Date discloses a first transistor electrically connected to the first select gate line (Fig. 12: each SGD is electrically connected to a transistor, see page 3, par. 0060);
a second transistor electrically connected to the second select gate line (Fig. 12: each SGD is electrically connected to a transistor, see page 3 , par. 0060);
a third transistor electrically connected to the third select gate line (Fig. 12: each SGD is electrically connected to a transistor, see page 3, par. 0060); and
a fourth transistor electrically connected to the fourth select gate line (Fig. 12: each SGS is electrically connected to a transistor, see page 3, par. 0060).
Regarding claim 3, Date discloses a third contact electrode disposed in the third region, the third contact electrode extending in the third direction and being connected to the first select gate line (Fig. 9: CCs are electrically connected to the MCAR comprising the plurality of select gate lines);
a fourth contact electrode disposed in the third region, the fourth contact electrode extending in the third direction and being connected to the second select gate line (Fig. 9: CCs are electrically connected to the MCAR comprising the plurality of select gate lines);
a fifth contact electrode disposed in the fourth region, the fifth contact electrode extending in the third direction and being connected to the third select gate line (Fig. 9: CCs are electrically connected to the MCAR comprising the plurality of select gate lines); and
a sixth contact electrode disposed in the fourth region, the sixth contact electrode extending in the third direction and being connected to the fourth select gate line (Fig. 9: CCs are electrically connected to the MCAR comprising the plurality of select gate lines).
Regarding claim 4, Date discloses a source line connected to the first semiconductor layer and the semiconductor layer (see page 3, par. 0057-0058).
Regarding claim 5, Date discloses a control circuit configured to perform a first erase operation (Fig. 4: VG, see page 3, par. 0062).
As discussed above, Date’s semiconductor memory device is substantially identical in structure to the claimed “semiconductor memory device,” where the differences reside only in the remaining limitations relating to function of “applying a first voltage to the first select gate line; applying a second voltage to the second select gate line; applying a third voltage to the third select gate line; and applying a fourth voltage to the fourth select gate line, wherein the first voltage is smaller than the third voltage, and the second voltage is smaller than the fourth voltage.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Date’s semiconductor memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 6, Date discloses a source line connected to the first semiconductor layer and the second semiconductor layer (see page 3, par. 0057-0058).
As discussed above, Date’s semiconductor memory device is substantially identical in structure to the claimed “semiconductor memory device,” where the differences reside only in the remaining limitations relating to function of “applying a first erase voltage larger than the first voltage and the second voltage to the first bit line; and applying a second erase voltage larger than the first voltage and the second voltage to the source line.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Date’s semiconductor memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 7, Date discloses a first source line connected to the first semiconductor layer; and
a second source line connected to the second semiconductor layer (Fig. 8 shows a plurality of memory blocks BLKs and each memory block comprises a source line connected to the semiconductor layers, see page 3, par. 0057).
Regarding claim 8, Date discloses a control circuit configured to perform a first erase operation (Fig. 4: VG, see page 3, par. 0062).
As discussed above, Date’s semiconductor memory device is substantially identical in structure to the claimed “semiconductor memory device,” where the differences reside only in the remaining limitations relating to function of “applying a first voltage to the first select gate line; applying a second voltage to the second select gate line; applying a third voltage to the third select gate line; and applying a fourth voltage to the fourth select gate line, wherein the first voltage is larger than the third voltage, and the second voltage is larger than the fourth voltage.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Date’s semiconductor memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 9, Date discloses a first source line connected to the first semiconductor layer; and a second source line connected to the second semiconductor layer (Fig. 8 shows a plurality of memory blocks BLKs and each memory block comprises a source line connected to the semiconductor layers, see page 3, par. 0057).
As discussed above, Date’s semiconductor memory device is substantially identical in structure to the claimed “semiconductor memory device,” where the differences reside only in the remaining limitations relating to function of “applying a first erase voltage larger than the first voltage and the second voltage to the first bit line; applying a fifth voltage smaller than the first erase voltage to the second bit line; applying a second erase voltage larger than the first voltage and the second voltage to the first source line; and applying a sixth voltage smaller than the second erase voltage to the second source line.”
The MPEP explains that examiners are to presume claimed functions are inherent when the prior art apparatus is substantially identical to the claimed apparatus. See esp. MPEP 2112.01(I) (Product and Apparatus Claims – When the Structure Recited in the Reference is Substantially Identically to that of the Claims, Claimed Properties or Functions Are Presumed to be Inherent). Date’s semiconductor memory device appears to be identical to applicant’s device, and thus the prior art apparatus is substantially identical to claimed apparatus, for which the claimed functions are presumed inherent. See MPEP 2112.01(I).
This presumption is rebuttable by applicant either (1) showing the prior art device and claimed device are not the same or (2) proving prior art device is incapable of performing the claimed functions. In re Ludtke, 441 F.2d 660, 664 (CCPA 1971); see MPEP 2112.01(I)(quoting In re Spada, 911 F.2d 705, 709 for “When the PTO shows a sound basis for believing that the products of the application and the prior art are the same, the applicant has the burden of showing that they are not.”). Applicant is reminded that argument of counsel is not evidence. MPEP 2145(I). Applicant is also reminded that claim limitations directed to the manner of operating do not distinguish an apparatus claim from the prior art apparatus. MPEP 2114(II) (“Manner of Operating the Device Does Not Differentiate Apparatus Claim from the Prior Art”).
Regarding claim 15, Date discloses a plurality of first memory cells disposed between the first select gate line and the second select gate line (Figs. 9 and 12: a plurality of memory cells connected to WLs are disposed between the select gates, see also page 7, par. 0116);
a plurality of second memory cells disposed between the third select gate line and the fourth select gate line (Figs. 9 and 12: a plurality of memory cells connected to WLs are disposed between the select gates, see also page 7, par. 0116); and
a control circuit configured to perform a first erase operation (Fig. 4: VG, see page 3, par. 0062) corresponding to an input of a first command set (see page 5, par. 0092), wherein
the first command set includes information to designate any one of the plurality of first memory cells or the plurality of second memory cells (see page 5, par. 0092).
Regarding claim 16, Date discloses a first memory block which is one of the plurality of memory blocks includes the plurality of first memory cells (Fig. 8: MCAR region comprises a plurality of blocks BLK comprising the plurality of memory cells), and
a second memory block which is another of the plurality of memory blocks includes the plurality of second memory cells (Fig. 8: MCAR region comprises a plurality of blocks BLK comprising the plurality of memory cells).
Allowable Subject Matter
Claims 10-14 and 17-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With respect to claim 10, there is no teaching or suggestion in the prior art of record to provide the recited substrate includes a fifth region farther from the fourth region than the first region; and a sixth region farther from the third region than the second region, and the plurality of memory blocks includes: a fifth select gate line that is disposed in the fifth region and farther from the substrate than the plurality of word lines; a sixth select gate line that is disposed in the fifth region and closer to the substrate than the plurality of word lines; a third semiconductor layer disposed in the fifth region, the third semiconductor layer extending in the third direction and being opposed to the plurality of word lines, the fifth select gate line, and the sixth select gate line; a seventh select gate line that is disposed in the sixth region and farther from the substrate than the plurality of word lines; an eighth select gate line that is disposed in the sixth region and closer to the substrate than the plurality of word lines; and a fourth semiconductor layer disposed in the sixth region, the fourth semiconductor layer extending in the third direction and being opposed to the plurality of word lines, the seventh select gate line, and the eighth select gate line, and the plurality of wirings in the wiring layer includes: a third bit line extending in the third direction, the third bit line being disposed at a position overlapping with the third semiconductor layer viewed in the third direction; and a fourth bit line extending in the third direction, the fourth bit line being disposed at a position overlapping with the fourth semiconductor layer viewed in the third direction.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALFREDO BERMUDEZ LOZADA whose telephone number is (571)272-0877. The examiner can normally be reached 7:00AM-3:30PM EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander G Sofocleous can be reached at 571-272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/Alfredo Bermudez Lozada/ Primary Examiner, Art Unit 2825