Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending in this action.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/18/2024 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 15-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park et al. (US 2022/0,113,889), in view of Sharma et al. (US 2022/0,122,682)
As per claim 1:
Park discloses:
A memory device comprising:
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
a memory core including a memory cell array including a plurality of memory cells, the memory cell array arranged into a plurality of memory banks;
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
(Park, Fig. 2, Memory Core with 4 banks)
(Park, [0072] The memory core 200 may include first to fourth bank arrays 122a, 122b, 122c, and 122d. The first to fourth bank arrays 122a, 122b, 122c, and 122d may correspond to the memory cell array 122 of FIG. 1.)
a Built-In Self-Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; and
(Park, Fig. 2, MBIST Circuit 127, BISR Control Circuit 128, Control Circuit 124)
(Park, [0074] The BIRA circuit 220 is correlated with the BISR control circuit 128 of the MBIST circuit 126. During a test for the first to fourth banks BANK1 to BANK4, when a failure of one of the banks is detected)
a control circuit configured to control the parallel test,
(Park, Claim 1, a method of testing a memory device including a plurality of memory banks and a memory built-in self-test (MBIST) circuit, wherein the plurality of memory banks include a plurality of memory cells, and the MBIST circuit performs a … a parallel bit test (PBT))
(Park [0102] … when the test mode option for a test to be performed in the MBIST circuit 126 is set to the PBT test mode, a PBT test for the memory device 120 may be performed (operation S320))
(Park [0103] During the PBT test in operation S320, operation S521 in which the TPG circuit 127 of the MBIST circuit 126 generates and sets PBT signals PBTS including a plurality of PBT patterns suitable for a PBT test may be performed)
(Park [0104] In operation S522, when the operation state of a first test pattern TP1 from among the PBT patterns is enabled, a PBT test for the first to fourth banks BANK1 to BANK4 is performed using the first test pattern)
wherein the BIST circuit is configured to determine one or more defective memory cell outputting a defective bit among a plurality of memory cells in the target memory bank, and
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
determine whether the defective memory cell is
a
or
an
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
the control circuit configured to determine the target memory bank to be a defective memory bank when the defective memory cell is not the
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
Park discloses a method of detecting fail-memory-cell. However, Park does not clearly disclose a method a single defective memory cell and/or adjacent double defective memory cell.
Sharma discloses a method of detecting
a single defective memory cell
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
and/or adjacent double defective memory cell.
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
(Sharma, Fig. 2 shows a method of MBIST performing parallel testing for plurality of memory 208 by a plurality of ECU 206 in order to correct/detect different error types)
(Sharma [0037] …memory BIST (MBIST) may be executed to detect correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time … the MBIST is generally run at-speed (at maximum speed), and covering multiple (or all) memories in parallel)(Sharma [0040] … error type (correctable/uncorrectable), error bit position, error address location, and memory identifiers, are sent to a central memory error management unit (MEMU) circuit in the form of error data packets (also referred to as error packets) for logging (storing) …)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate ECC of Sharma into the system of Park in order so it is capable of correcting single-bit-error or double-bit errors and detecting a triple bit-errors. Therefore, the system would able to resolver bit errors using ECC of Sharama.
(Sharma, [0062] ECC is capable of correcting double-bit errors and detecting triple-bit errors)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
As per claim 2:
Park-Sharma further discloses:
wherein the BIST circuit is configured to determine an output bit that is in a logical state different from an input bit, among output bits output from the target memory cells, as the defective bit.
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
As per claim 3:
Park-Sharma further discloses:
wherein the BIST circuit comprises a first test circuit configured to determine the defective memory cell, a second test circuit configured to determine whether the defective memory cell is
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
Sharma further discloses a method of detecting a single defective memory cell (Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection) and/or adjacent double defective memory cell. (Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
(Sharma, Fig. 2 shows a method of MBIST performing parallel testing for plurality of memory 208 by a plurality of ECU 206 in order to correct/detect different error types)
(Sharma [0037] …memory BIST (MBIST) may be executed to detect correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time … the MBIST is generally run at-speed (at maximum speed), and covering multiple (or all) memories in parallel)
(Sharma [0040] … error type (correctable/uncorrectable), error bit position, error address location, and memory identifiers, are sent to a central memory error management unit (MEMU) circuit in the form of error data packets (also referred to as error packets) for logging (storing) …)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
In view of motivation previously stated, the claim is rejected.
As per claim 4:
Park-Sharma further discloses:
wherein when one memory cell among the target memory cells outputs the defective bit, the second test circuit determines the one memory cell to be the
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
Sharma further discloses a method of detecting a single defective memory cell (Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection) and/or adjacent double defective memory cell. (Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
(Sharma, Fig. 2 shows a method of MBIST performing parallel testing for plurality of memory 208 by a plurality of ECU 206 in order to correct/detect different error types)
(Sharma [0037] …memory BIST (MBIST) may be executed to detect correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time … the MBIST is generally run at-speed (at maximum speed), and covering multiple (or all) memories in parallel)
(Sharma [0040] … error type (correctable/uncorrectable), error bit position, error address location, and memory identifiers, are sent to a central memory error management unit (MEMU) circuit in the form of error data packets (also referred to as error packets) for logging (storing) …)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
In view of motivation previously stated, the claim is rejected.
As per claim 5:
Park-Sharma further discloses:
wherein each of the plurality of memory banks includes a plurality of word lines and a plurality of bit lines, and the plurality of memory cells are connected to the plurality of word lines and the plurality of bit lines, and the pair of memory cells are connected to one word line among the plurality of word lines and a pair of adjacent bit lines adjacent to each other among the plurality of bit lines.
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
As per claim 6:
Park-Sharma further discloses:
wherein the pair of bit lines is determined by the control circuit.
(Park, Fig. 2, MBIST Circuit 127, BISR Control Circuit 128, Control Circuit 124)
As per claim 15:
Park discloses:
A memory device comprising:
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
a memory core including a memory cell array including a plurality of memory cells, the memory cell array being divided into a plurality of memory banks;
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
(Park, Fig. 2, Memory Core with 4 banks)
(Park, [0072] The memory core 200 may include first to fourth bank arrays 122a, 122b, 122c, and 122d. The first to fourth bank arrays 122a, 122b, 122c, and 122d may correspond to the memory cell array 122 of FIG. 1.)
a Built-In Self Test (BIST) circuit configured to select a target memory bank from the plurality of memory banks and perform a parallel test on the target memory bank among the plurality of memory banks; and
(Park, Fig. 2, MBIST Circuit 127, BISR Control Circuit 128, Control Circuit 124)
(Park, [0074] The BIRA circuit 220 is correlated with the BISR control circuit 128 of the MBIST circuit 126. During a test for the first to fourth banks BANK1 to BANK4, when a failure of one of the banks is detected)
a control circuit configured to control the parallel test, wherein the BIST circuit includes, for target memory cells included in the target memory bank,
(Park, Claim 1, a method of testing a memory device including a plurality of memory banks and a memory built-in self-test (MBIST) circuit, wherein the plurality of memory banks include a plurality of memory cells, and the MBIST circuit performs a … a parallel bit test (PBT))
(Park [0102] … when the test mode option for a test to be performed in the MBIST circuit 126 is set to the PBT test mode, a PBT test for the memory device 120 may be performed (operation S320))
(Park [0103] During the PBT test in operation S320, operation S521 in which the TPG circuit 127 of the MBIST circuit 126 generates and sets PBT signals PBTS including a plurality of PBT patterns suitable for a PBT test may be performed)
(Park [0104] In operation S522, when the operation state of a first test pattern TP1 from among the PBT patterns is enabled, a PBT test for the first to fourth banks BANK1 to BANK4 is performed using the first test pattern)
a first test circuit configured to determine a defective memory cell and output a first output signal, a second test circuit configured to determine whether the defective memory cell is a s
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
a third test circuit configured to determine whether the defective memory cell is an
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
wherein the control circuit is configured to determine the target memory bank to be a defective memory bank when the defective memory cell is not the
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
Park discloses a method of detecting fail-memory-cell.
However, Park does not clearly disclose a method of detecting different type of fail-memory-cell such as single defective memory cell and/or adjacent double defective memory cell and/or NOT single or double defective memory cell
Sharma discloses a method of detecting different type of fail-memory-cell such as single defective memory cell and/or adjacent double defective memory cell and/or NOT single or double defective memory cell
(It is noted that when it is NOT a single bit error and/or double bit error, then it must be a triple-bit error or quad-bit errors)
(Sharma, Fig. 2 shows a method of MBIST performing parallel testing for plurality of memory 208 by a plurality of ECU 206 in order to correct/detect different error types)
(Sharma [0037] …memory BIST (MBIST) may be executed to detect correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time … the MBIST is generally run at-speed (at maximum speed), and covering multiple (or all) memories in parallel)
(Sharma [0040] … error type (correctable/uncorrectable), error bit position, error address location, and memory identifiers, are sent to a central memory error management unit (MEMU) circuit in the form of error data packets (also referred to as error packets) for logging (storing) …)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate ECC of Sharma into the system of Park in order so it is capable of correcting single-bit-error or double-bit errors and detecting a triple bit-errors. Therefore, the system would able to resolver bit errors using ECC of Sharama.
(Sharma, [0062] ECC is capable of correcting double-bit errors and detecting triple-bit errors)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
As per claim 16:
Park-Sharma further discloses:
wherein the target memory cells are divided into a plurality of regions, and the BIST circuit is configured to output the first output signal to the third output signal for each of the plurality of regions.
(Park, [0072] The memory core 200 may include first to fourth bank arrays 122a, 122b, 122c, and 122d. The first to fourth bank arrays 122a, 122b, 122c, and 122d may correspond to the memory cell array 122 of FIG. 1.)
As per claim 17:
Park-Sharma further discloses:
wherein the first test circuit determines at least one memory cell outputting a logic state different from an input bit, among the target memory cells, as the defective memory cell, and outputs the first output signal in a second state with respect to a region including the defective memory cell, among the plurality of regions.
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
As per claim 18:
Park-Sharma further discloses:
wherein when one memory cell among the target memory cells outputs the logic state different from the input bit, the second test circuit determines the one memory cell to be the single defective memory cell, and outputs the second output signal in a first state with respect to a region including the
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
As per claim 19:
Park-Sharma further discloses:
wherein the control circuit determines the target memory bank to be a defective memory bank when the second output signal and the third output signal are not output in the first state, with respect to at least one region among the plurality of regions in which the first output signal is output in a second state.
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
As per claim 20:
Park discloses:
A test method for a memory device including a plurality of memory banks, the method comprising:
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
selecting a target memory bank from the plurality of memory banks, and determining a defective memory cell outputting a logic state different from an input bit among target memory cells included in the target memory bank;
(Park, Fig. 1, System 10, Memory Device 120, Memory Cell Array 122)
(Park, Fig. 2, Memory Core with 4 banks)
(Park, [0072] The memory core 200 may include first to fourth bank arrays 122a, 122b, 122c, and 122d. The first to fourth bank arrays 122a, 122b, 122c, and 122d may correspond to the memory cell array 122 of FIG. 1.)
when the defective memory cell is determined among the target memory cells,
determining whether the defective memory cell is a
(Park [0112] In operation S610, when a defective cell is detected during a … or a PBT test by the MBIST circuit 126, the control circuit 124 may output the fail flag signal FS and the fail cell address F/A. The fail flag signal FS may be provided to the BISR control circuit 128 of the MBIST circuit 126, and the fail cell address F/A may be stored in an address storage table 222 of the BIRA circuit 220. In operation S610, when no fail cell is detected, an MBIST may be terminated)
Park discloses a method of detecting fail-memory-cell.
However, Park does not clearly disclose a method of detecting different type of fail-memory-cell such as single defective memory cell and/or adjacent double defective memory cell and/or NOT single or double defective memory cell
Sharma discloses a method of detecting different type of fail-memory-cell such as single defective memory cell and/or adjacent double defective memory cell and/or NOT single or double defective memory cell
(It is noted that when it is NOT a single bit error and/or double bit error, then it must be a triple-bit error or quad-bit errors)
(Sharma, Fig. 2 shows a method of MBIST performing parallel testing for plurality of memory 208 by a plurality of ECU 206 in order to correct/detect different error types)
(Sharma [0037] …memory BIST (MBIST) may be executed to detect correctable and uncorrectable error locations in each memory. Since it is generally desirable to minimize the time … the MBIST is generally run at-speed (at maximum speed), and covering multiple (or all) memories in parallel)
(Sharma [0040] … error type (correctable/uncorrectable), error bit position, error address location, and memory identifiers, are sent to a central memory error management unit (MEMU) circuit in the form of error data packets (also referred to as error packets) for logging (storing) …)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
It would have been obvious before the effective filing date of the claimed to a person having ordinary skill in the art to incorporate ECC of Sharma into the system of Park in order so it is capable of correcting single-bit-error or double-bit errors and detecting a triple bit-errors. Therefore, the system would able to resolver bit errors using ECC of Sharama.
(Sharma, [0062] ECC is capable of correcting double-bit errors and detecting triple-bit errors)
(Sharma [0042]…MBIST…four types of error packets associated with non-volatile memories (e.g., single/double/tripler error correction, and multiple error detection)
Allowable Subject Matter
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 8-14 are also objected due to dependency of objected claim 7.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record do not mention about a plurality of half adders…such as “wherein the third test circuit includes an input unit, a logic unit including a plurality of half adders, and an output unit for outputting an output signal, wherein the input unit is configured to receive a selection signal for determining the pair of bit lines from the control circuit and bit determination signals indicating whether each of the output bits is a defective bit from the first test circuit, and output the bit determination signals corresponding to the pair of memory cells, among the bit determination signals, to each of the plurality of half adders, the logic unit is configured to output a first internal signal to a third internal signal using the bit determination signals corresponding to the pair of memory cells, and the output unit configured to output an output signal indicating whether the pair of memory cells are the adjacent double defective memory cell using the first internal signal to the third internal signal” as recited in claim 7.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li et al. (US 2022/0,012,125) in [0047] discloses that …each column includes eight (8) memory cells (e.g., 8 bits of data), there may be eight (8) single bit error possibilities and seven (7) double bit error possibilities (e.g., when the double bit errors are in adjacent components). … there may be additional errors that were detected during the test operation (e.g., an error at the first (bit 0) and eighth (bit 7) bit locations) beyond the fifteen (15) possibilities. … detect an absence of errors in the memory array…
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THIEN DANG NGUYEN whose telephone number is (571)272-9189. The examiner can normally be reached Monday-Friday 7 AM - 3:30 PM.
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/Thien Nguyen/ Primary Examiner, Art Unit 2111