DETAILED ACTION
Response to Amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4-9, 11-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Urade et al. (U.S. Patent Number 6,272,644) and Shon et al. (U.S. Patent Application Publication Number 2019/0214989).
Regarding Claim 1, Urade discloses a method of implementing logic retention support in a data processing system comprising:
distributing, based on a logic retention power mode request (Column 4, lines 57-60; i.e., based on how the term “logic retention” is defined in the specification [paragraph 0001], the suspend request is equated to the “logic retention power mode request”; a suspend power state is known in the art to retain data in a low power mode as evidenced by the attached article “System Power Management Sleep States”), one or more secondary requests (Column 4, lines 60-65; i.e., passing the suspend request to other devices such as peripherals and the microcontroller) to functional units in the power domain, said distributing including:
mapping the logic retention power mode request to a clock quiescence request (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the suspend request is “mapped” to the stop clock signal [the claimed “clock quiescence request”] because they have a relationship in which every time the suspend request is sent, the stop clock signal is also sent);
distributing the clock quiescence request to one or more first functional units of the functional units (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the stop clock signal is sent to the USB hub 11); and
maintaining the one or more first functional units in a functional power mode (Column 6, lines 4-15; i.e., the USB hub 11 is placed in a mode in which it is easily awoken by the microcontroller [the claimed “functional power mode”]), where logic of the one or more first functional units remains powered on and functional while a clock of the one or more first functional units is quiesced in response to the clock quiescence request (Column 4, line 66 - Column 5, line 9 and Column 5, line 63 - Column 6, line 16; i.e., at least some logic within the hub must remain on and functional in order for it to receive the RESUMEI signal from the microcontroller, relay the resume signal to the host computer, and release the suspend signal sent to the microcontroller all before the clock is restarted).
Urade does not expressly disclose that the one or more first functional units are without a logic retention power mode.
In the same field of endeavor (e.g., clock control techniques), Shon teaches that the one or more first functional units (Figure 8, item 200) are without a logic retention power mode (paragraphs 0141-0142; i.e., the first functional unit 200 is without a logic retention power mode and therefore must have its clock gated, whereas the device 412 supports the retention mode).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Shon’s teachings of clock control techniques with the teachings of Urade, for the purpose of allowing different types of devices (e.g., devices that support and do not support the retention mode) to save power. This is achieved by incorporating Shon’s different devices shown in Figure 8 into the system as shown in Figure 3 of Urade.
Regarding Claim 2, Urade discloses distributing the logic retention power mode request to one or more second functional units that support the logic retention power mode (Column 4, lines 60-61; i.e., the suspend request is sent to the peripheral devices).
Regarding Claim 4, Urade discloses sending, to the one or more first functional units, a request to enter one of an ON type functional power mode (Column 6, lines 4-6; i.e., a resume signal), an OFF type non-functional power mode, a memory retention power mode, or a power quiescence mode, where the request excludes an explicit clock quiescence request.
Regarding Claim 5, Urade discloses applying said clock quiescence request to selected units of the one or more first functional units; and requesting the selected units to enter clock quiescence (Column 4, lines 62-64 and Column 5, lines 40-50).
Regarding Claim 6, Urade discloses driving, by clock controllers, in response to the clock quiescence request, the one or more first functional units to a clock quiescent state (Column 4, lines 62-64 and Column 5, lines 40-50).
Regarding Claim 7, Urade discloses providing the logic retention power mode request to a sequencing unit (Figure 4, item 12, Column 4, lines 57-60; i.e., it performs the suspend and clock gating operations in a particular sequence).
Regarding Claim 8, Urade discloses a system comprising:
a power controller (Column 4, lines 57-60; i.e., the host computer acts as a power controller since it controls the power of the USB hub 11 and connected devices) of a power domain configured to provide a logic retention power mode request (Column 4, lines 57-60; i.e., based on how the term “logic retention” is defined in the specification [paragraph 0001], the suspend request is equated to the “logic retention power mode request”; a suspend power state is known in the art to retain data in a low power mode as evidenced by the attached article “System Power Management Sleep States”) to a distributor (Figure 3, item 12); and
the distributor configured to:
distribute one or more secondary requests to functional units in the power domain in response to receipt of the logic retention power mode request (Column 4, lines 60-65; i.e., passing the suspend request to other devices such as peripherals and the microcontroller), said distributing further configured to:
map the logic retention power mode request to a clock quiescence request (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the suspend request is “mapped” to the stop clock signal [the claimed “clock quiescence request”] because they have a relationship in which every time the suspend request is sent, the stop clock signal is also sent);
distribute the clock quiescence request to one or more first functional units of the functional units (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the stop clock signal is sent to the USB hub 11); and
maintain the one or more first functional units in a functional power mode (Column 6, lines 4-15; i.e., the USB hub 11 is placed in a mode in which it is easily awoken by the microcontroller [the claimed “functional power mode”]), where logic of the one or more first functional units remains powered on and functional while a clock of the one or more first functional units is quiesced in response to the clock quiescence request (Column 4, line 66 - Column 5, line 9 and Column 5, line 63 - Column 6, line 16; i.e., at least some logic within the hub must remain on and functional in order for it to receive the RESUMEI signal from the microcontroller, relay the resume signal to the host computer, and release the suspend signal sent to the microcontroller all before the clock is restarted).
Urade does not expressly disclose that the one or more first functional units are without a logic retention power mode.
In the same field of endeavor, Shon teaches that the one or more first functional units (Figure 8, item 200) are without a logic retention power mode (paragraphs 0141-0142; i.e., the first functional unit 200 is without a logic retention power mode and therefore must have its clock gated, whereas the device 412 supports the retention mode).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 8.
Regarding Claim 9, Urade discloses where the distributor is further configured to distribute the logic retention power mode request to one or more second functional units that support the logic retention power mode (Column 4, lines 60-61; i.e., the suspend request is sent to the peripheral devices).
Regarding Claim 11, Urade discloses where the power controller is further configured to send, to the one or more first functional units, a request to enter one of an ON type functional power mode (Column 6, lines 4-6; i.e., a resume signal), an OFF type non-functional power mode, a memory retention power mode, or a power quiescence mode, where the request excludes an explicit clock quiescence request.
Regarding Claim 12, Urade discloses where the power controller is further configured to send, to the one or more first functional units, a request to enter an “ON” mode (Column 6, lines 4-6; i.e., a resume signal), where the request excludes an explicit clock quiescence request.
Regarding Claim 13, Urade discloses where said clock quiescence request is applied to selected units of the one or more first functional units; and the selected units are requested to enter clock quiescence (Column 4, lines 62-64 and Column 5, lines 40-50).
Regarding Claim 14, Urade discloses clock controllers configured to drive the one or more first functional units to a clock quiescent state in response to the clock quiescence request (Column 4, lines 62-64 and Column 5, lines 40-50).
Regarding Claim 15, Urade discloses where the distributor is a sequencer (Figure 4, item 12, Column 4, lines 57-60; i.e., it performs the suspend and clock gating operations in a particular sequence).
Regarding Claim 16, Urade discloses a non-transitory computer-readable medium (Column 6, lines 44-54; i.e., the algorithm for the method must be stored on a computer-readable medium in order to be executed) to store computer-readable code for fabrication of a logic retention support circuit of a data processing system, the logic retention support circuit configured to:
receive a logic retention power mode request (Column 4, lines 57-60; i.e., based on how the term “logic retention” is defined in the specification [paragraph 0001], the suspend request is equated to the “logic retention power mode request”; a suspend power state is known in the art to retain data in a low power mode as evidenced by the attached article “System Power Management Sleep States”);
distribute, based on the logic retention power mode request, one or more secondary requests to functional units in a power domain (Column 4, lines 60-65; i.e., passing the suspend request to other devices such as peripherals and the microcontroller), said distributing further configured to:
map the logic retention power mode request to a clock quiescence request (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the suspend request is “mapped” to the stop clock signal [the claimed “clock quiescence request”] because they have a relationship in which every time the suspend request is sent, the stop clock signal is also sent);
distribute the clock quiescence request to one or more first functional units of the functional units (Column 4, lines 62-64 and Column 5, lines 40-50; i.e., the stop clock signal is sent to the USB hub 11); and
maintain the one or more first functional units in a functional power mode (Column 6, lines 4-15; i.e., the USB hub 11 is placed in a mode in which it is easily awoken by the microcontroller [the claimed “functional power mode”]), where logic of the one or more first functional units remains powered on and functional while a clock of the one or more first functional units is quiesced in response to the clock quiescence request (Column 4, line 66 - Column 5, line 9 and Column 5, line 63 - Column 6, line 16; i.e., at least some logic within the hub must remain on and functional in order for it to receive the RESUMEI signal from the microcontroller, relay the resume signal to the host computer, and release the suspend signal sent to the microcontroller all before the clock is restarted).
Urade does not expressly disclose that the one or more first functional units are without a logic retention power mode.
In the same field of endeavor, Shon teaches that the one or more first functional units (Figure 8, item 200) are without a logic retention power mode (paragraphs 0141-0142; i.e., the first functional unit 200 is without a logic retention power mode and therefore must have its clock gated, whereas the device 412 supports the retention mode).
The motivation discussed above with regards to Claim 1 applies equally as well to Claim 16.
Regarding Claim 17, Urade discloses where the logic retention support circuit is further configured to distribute the logic retention power mode request to one or more second functional units that support the logic retention power mode (Column 4, lines 60-61; i.e., the suspend request is sent to the peripheral devices).
Regarding Claim 19, Urade discloses where the computer readable code includes code for fabrication of a logic retention support circuit further configured to send, to the one or more first functional units, a request to enter one of an ON type functional power mode (Column 6, lines 4-6; i.e., a resume signal), an OFF type non-functional power mode, a memory retention power mode, or a power quiescence mode, where the request excludes an explicit clock quiescence request.
Regarding Claim 20, Urade discloses where the one or more first functional units are not requested to enter a logic retention power mode, an OFF power mode, or a power quiescence (Column 4, lines 57-65; i.e., the hub is requested to enter the suspend mode, in which power remains partially on, rather than any of the claimed modes).
Claims 3, 10, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Urade and Shon as applied to claims 1, 8, and 16 above, and further in view of Nam et al. (U.S. Patent Number 11,176,985).
Regarding Claim 3, Urade discloses distributing the logic retention power mode request to one or more third functional units; and mapping, for the one or more third functional units, the logic retention power mode request to a power quiescence request (Column 4, lines 57-61 and Column 5, lines 40-43; i.e., the suspend request [the “logic retention power mode request”] and is sent to the microcontroller [the claimed “third functional unit”] where it is mapped to a power quiescence request [a request to stop all I2C activity]).-
Urade and Shon do not expressly disclose the one or more third functional units control power domain boundary crossings of the power domain.
In the same field of endeavor (e.g., power control techniques), Nam teaches the one or more third functional units control power domain boundary crossings of the power domain (Column 5, lines 49-53).
Accordingly, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have combined Nam’s teachings of power control techniques with the teachings of Urade and Shon, for the purpose of allowing devices conforming to the different power requirements to be able to communicate with one another.
Regarding Claim 10, Urade discloses where the distributor is further configured to: distribute the logic retention power mode request to one or more third functional units; and map, for the one or more third functional units, the logic retention power mode request to a power quiescence request (Column 4, lines 57-61 and Column 5, lines 40-43; i.e., the suspend request [the “logic retention power mode request”] and is sent to the microcontroller [the claimed “third functional unit”] where it is mapped to a power quiescence request [a request to stop all I2C activity]).
Urade and Shon do not expressly disclose the one or more third functional units control power domain boundary crossings of the power domain.
In the same field of endeavor, Nam teaches the one or more third functional units control power domain boundary crossings of the power domain (Column 5, lines 49-53).
The motivation discussed above with regards to Claim 3 applies equally as well to Claim 10.
Regarding Claim 18, Urade discloses where the computer readable code includes code for fabrication of a logic retention support circuit further configured to distribute the logic retention power mode request to one or more third functional units; and map, for the one or more third functional units, the logic retention power mode request to a power quiescence request (Column 4, lines 57-61 and Column 5, lines 40-43; i.e., the suspend request [the “logic retention power mode request”] and is sent to the microcontroller [the claimed “third functional unit”] where it is mapped to a power quiescence request [a request to stop all I2C activity]).
Urade and Shon do not expressly disclose the one or more third functional units control power domain boundary crossings of the power domain.
In the same field of endeavor, Nam teaches the one or more third functional units control power domain boundary crossings of the power domain (Column 5, lines 49-53).
The motivation discussed above with regards to Claim 3 applies equally as well to Claim 18.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference discloses a method for implementing logic retention support in a processing system.
Response to Arguments
Applicant's arguments filed 7/21/26 have been fully considered but they are not persuasive.
Regarding Claim 1, Applicant argues “Urade further confirms that the hub is not functional in this condition, describing waking ‘the USB hub through the interface despite the lack of a clock signal in the suspend mode.’ Urade, column 6, lines 14-16. Thus, instead of the logic of the first functional unit ‘remain[ing] powered on and functional’ while only its clock is quiesced-as claims 1, 8, and 16 now clarify-Urade stops the clock precisely in order to place the unit in a suspend/powersave state in which it cannot operate.” Response, page 10. The examiner disagrees. Contrary to Applicant’s argument, Urade does in fact disclose the claimed limitation. The claim requires “where logic of the one or more first functional units remains powered on and functional”. This could be taken to mean that some logic of the one or more first functional units remains powered on and functional.
Urade states “[i]f an external non-USB source, such as an IR remote control, instructs the microcontroller to turn on, the microcontroller sends a resume request to the USB hub (11) using a resume signal. The USB hub (11) relays this request to the host computer. In response to the received resume request the USB hub releases the suspend signal sent to the microcontroller. In response to the released suspend signal the microcontroller releases the stop clock signal sent to the USB hub and the process, discussed below in connection with FIGS. 5 and 6, is followed to wake up the microcontroller.” Urade, Column 4, line 66 - Column 5, line 9.
Urade further states “[t]he hub controller (28) sends a SUSPEND signal to the microcontroller (29) at a time t.sub.1 in response to a suspend request from a host computer (not shown) connected to the hub controller. In response to this received SUSPEND request, the microcontroller asserts a STOPCLK signal to the hub controller at a time t.sub.2. The microcontroller then enters the STOP, or powersave, mode. In this mode the CLK signal from the oscillator (23), shown in FIG. 3, is stopped at time t.sub.2. At a time t.sub.3 the microcontroller asserts a RESUMEI signal to the hub controller to wake up the USB hub (11). In response to the received RESUMEI signal, at time t.sub.4 the hub controller de-asserts the SUSPEND signal sent to the microcontroller. In response, the microcontroller de-asserts the RESUMEI signal at time t.sub.5 to the hub controller. Also at time t.sub.5, in response to the de-assertion of the SUSPEND signal sent to the microcontroller, the microcontroller de-asserts the STOPCLK signal sent to the hub controller. The de-assertion of the STOPCLK signal causes the oscillator (23) of the hub controller to restart. In this manner, the microcontroller is able to wake up the USB hub through the interface despite the lack of a clock signal in the suspend mode.” Id. at Column 5, line 63 - Column 6, line 16.
Both of these statements indicate that there is some logic within the USB hub 11 that “remains powered on and functional” while its clock is quiesced, because the USB hub 11 performs various functions such as relaying the resume signal to the host computer and releasing the suspend signal sent to the microcontroller before the clock is resumed. Accordingly, it can be seen that Urade does in fact disclose the argued feature.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning (Response, page 11), it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Regarding Claim 3, Applicant argues “Nam therefore does not teach, disclose or suggest a functional unit that controls power-domain boundary crossings and receives the logic retention request remapped to a power quiescence request”. Response, page 12. The examiner disagrees. Nam states “[t]he detection of the threshold values during the reduced power mode can trigger protection signals to protect the floating VPD signals from causing undesirable increased standby current due to power domain boundary crossings.” Nam, Column 5, lines 49-53. This is equivalent to the claimed feature of “one or more third functional units control power domain boundary crossings of the power domain”. In addition, as discussed in the § 103 rejection above, Urade discloses the claimed feature of “distributing the logic retention power mode request to one or more third functional units; and mapping, for the one or more third functional units, the logic retention power mode request to a power quiescence request”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Therefore, the claims stand as previously rejected.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAISAL M ZAMAN whose telephone number is (571)272-6495. The examiner can normally be reached Monday - Friday, 8 am - 5 pm, alternate Fridays.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrew J. Jung can be reached at 571-270-3779. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/FAISAL M ZAMAN/ Primary Examiner, Art Unit 2175
Prosecution Insights