Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Deen et al. (US 20220037313 A1) in view of Richard et al. (US 20210372818 A1).
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CLAIM 1. Deen teaches a confinement apparatus package comprising:
one or more confinement apparatus dies having a respective plurality of electrodes formed thereon, wherein the respective plurality of electrodes defines a confinement apparatus (Deen ¶5-85 & Fig. 4A-B; ion trap chip 400A - ¶41 "The upper surface of the ion trap apparatus 400A comprises an ion trap chip 402A (e.g., surface ion trap chip) having a plurality of electrodes");
one or more application-specific integrated circuit (ASIC) chips comprising a respective ASIC die having a respective ASIC formed thereon (integrated switching apparatus/network chip 315, 420B, 515 is an ASIC chip; ¶38 - 41; Figs. 4A, 4B, 5; claim 1);
wherein: the respective ASIC die is disposed between the package substrate and the respective confinement apparatus die (integrated switching apparatus/network chip 315, 420B, 515 is arranged below the ion trap chip 402A, thus would be located between the confinement die and any other substrate on which it would be placed.; ¶38-39; Figs. 4A, 4B, 5), and
the respective ASIC defines a plurality of electrical channels and each electrode of the respective plurality of electrodes is in electrical communication with a respective electrical channel of the plurality of electrical channels ( ¶39-41]; Figs. 1A, 1B, 4A, 4B, 5, 6).
Deen may be silent regarding the specific option to stack the confinement/sensor die and the ASIC die on a package substrate; however, such a configuration would have been an obvious variation to a Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention.
Richard teaches a sensor die stacked on an ASIC die, which is further disposed on a package substrate to complete the device (Richard, Fig. 1, showing sensor chip 104 stacked on ASIC chip 102, which is located on package substrate 100). Richard explicitly teaches that this packaged, stacked configuration provides necessary structural protection, housing, and external electrical leads for the device.
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It would have been obvious to a PHOSITA at the time of the invention to modify the device of Deen by incorporating the substrate packaging techniques taught by Richard. A PHOSITA would have been motivated to combine these teachings to provide structural protection, environmental housing, and external electrical connections for Deen's sensor and ASIC dies, which are well-known benefits of standard semiconductor packaging. The modification represents the application of a known technique (Richard's substrate packaging) to a known device ready for improvement (Deen's sensor/ASIC arrangement) to yield predictable results (a protected, electrically interconnected packaged device). Therefore, the claimed subject matter is unpatentable under 35 U.S.C. § 103 (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007)).
CLAIM 2. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein the respective electrical channel comprises at least one shunt capacitor (Deen ¶55-85).
CLAIM 3. Deen in view of Richard teaches the confinement apparatus package of claim 2, wherein the at least one shunt capacitor is a trench capacitor (Deen ¶55-85).
CLAIM 4. Deen in view of Richard teaches the confinement apparatus package of claim 2, wherein the at least one shunt capacitor is formed one on of (a) the respective confinement apparatus die or (b) the respective ASIC chip (Deen ¶55-85).
CLAIM 5. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is in electrical communication with a second portion of the respective electrical channel disposed on the respective confinement apparatus die, at least in part, via one of (a) a through silicon via (TSV) formed in the respective confinement apparatus die (Deen Fig. 6) or (b) a wire bond (Deen Figs. 4-6 & ¶55-58).
CLAIM 6. Deen in view of Richard teaches the confinement apparatus package of claim 1, further comprising one or more interposer chips, a respective interposer chip disposed between the respective ASIC chip and the respective confinement apparatus die (Deen Figs. 4A-B)..
CLAIM 7. Deen in view of Richard teaches the confinement apparatus package of claim 6, wherein the respective electrical channel comprises at least one shunt capacitor and the at least one shunt capacitor is formed on the respective interposer chip (Deen Figs. 4-6 & ¶55-58).
CLAIM 8. Deen in view of Richard teaches the confinement apparatus package of claim 6, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is in electrical communication with a third portion of the respective electrical channel disposed on the respective interposer chip, at least in part, via one of (a) a through silicon via (TSV) formed in an interposer die of the respective interposer chip or (b) a wire bond (Deen Figs. 4-6 & ¶55-58).
CLAIM 9. Deen in view of Richard teaches the confinement apparatus package of claim 6, wherein a third portion of the respective electrical channel disposed on the respective interposer chip is in electrical communication with a second portion of the respective electrical channel disposed on the respective confinement apparatus die, at least in part, via one of (a) a through silicon via (TSV) formed in the respective confinement apparatus die of the respective confinement apparatus chip or (b) a wire bond (Deen Figs. 4-6 & ¶55-58).
CLAIM 10. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is configured to condition a voltage signal applied to one or more electrodes of the respective plurality of electrodes in electrical communication with the respective electrical channel (Deen Figs. 4-6 & ¶55-58).
CLAIM 11. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein the package substrate is at least one of a ceramic package or a printed circuit board (Deen Figs. 4-6 & ¶55-58 as modified by Richard – See regarding claim 1 teaching a package substate.).
CLAIM 12. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is in electrical communication with a preliminary portion of the respective electrical channel disposed on the package substrate(Deen Figs. 4-6 & ¶55-58).
CLAIM 13. Deen in view of Richard teaches the confinement apparatus package of claim 1, wherein the confinement apparatus is a surface ion trap (Deen Figs. 4-6 & ¶55-58).
CLAIM 14. Deen in view of Richard teaches the confinement apparatus package comprising: one or more confinement apparatus dies each having a respective plurality of electrodes formed thereon, wherein the respective plurality of electrodes defines a confinement apparatus (Deen Figs. 4-6 & ¶55-58);
one or more ASIC chips each comprising a respective application-specific integrated circuit (ASIC) die having a respective ASIC formed thereon (Deen Figs. 4-6 & ¶55-58);
at least one interposer chip (Deen Figs. 4-6 & ¶55-58); and
wherein: the at least one interposer chip is disposed between the respective ASIC die and the package substrate, the at least one interposer chip is disposed between the respective confinement apparatus die and the package substrate (integrated switching apparatus/network chip 315, 420B, 515 is arranged below the ion trap chip 402A, thus would be located between the confinement die and any other substrate on which it would be placed.; ¶38-39; Figs. 4A, 4B, 5), and the respective ASIC defines a plurality of electrical channels and each electrode of the respective plurality of electrodes is in electrical communication with a respective electrical channel of the plurality of electrical channels (Deen Figs. 4-6 & ¶55-58).
Deen may be silent regarding the specific option to stack the confinement/sensor die and the ASIC die on a package substrate; however, such a configuration would have been an obvious variation to a Person Having Ordinary Skill in the Art (PHOSITA) at the time of the invention.
Richard teaches a sensor die stacked on an ASIC die, which is further disposed on a package substrate to complete the device (Richard, Fig. 1, showing sensor chip 104 stacked on ASIC chip 102, which is located on package substrate 100). Richard explicitly teaches that this packaged, stacked configuration provides necessary structural protection, housing, and external electrical leads for the device.
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It would have been obvious to a PHOSITA at the time of the invention to modify the device of Deen by incorporating the substrate packaging techniques taught by Richard. A PHOSITA would have been motivated to combine these teachings to provide structural protection, environmental housing, and external electrical connections for Deen's sensor and ASIC dies, which are well-known benefits of standard semiconductor packaging. The modification represents the application of a known technique (Richard's substrate packaging) to a known device ready for improvement (Deen's sensor/ASIC arrangement) to yield predictable results (a protected, electrically interconnected packaged device). Therefore, the claimed subject matter is unpatentable under 35 U.S.C. § 103 (KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007)).
CLAIM 15. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein the respective confinement apparatus die and the respective ASIC chip are laterally arranged with respect to one another (Deen Figs. 4-6 & ¶55-58).
CLAIM 16. Deen in view of Richard teaches the confinement apparatus package of claim 15, further comprising one or more shunt capacitor chips each comprising a respective plurality of shunt capacitors formed on a respective shunt capacitor die, wherein the at least one interposer chip is disposed between the respective shunt capacitor chip and the package substrate (Deen Figs. 4-6 & ¶55-58).
CLAIM 17. Deen in view of Richard teaches the confinement apparatus package of claim 16, wherein each shunt capacitor of the respective plurality of shunt capacitors is part of a respective channel of the plurality of electrical channels(Deen Figs. 4-6 & ¶55-58).
CLAIM 18. Deen in view of Richard teaches the confinement apparatus package of claim 17, wherein at least one shunt capacitor of the respective plurality of shunt capacitors is a trench capacitor (Deen Figs. 4-6 & ¶55-58).
CLAIM 19. Deen in view of Richard teaches the confinement apparatus package of claim 17, wherein each of the respective confinement apparatus die, the respective ASIC chip, and the respective shunt capacitor chip are laterally arranged with respect to one another (Deen Figs. 4-6 & ¶55-58).
CLAIM 20. Deen in view of Richard teaches the confinement apparatus package of claim 17, wherein the respective shunt capacitor chip is flip chip mounted to the at least one interposer chip (Deen Figs. 4-6 & ¶55-58).
CLAIM 21. Deen in view of Richard teaches the confinement apparatus package of claim 15, wherein the respective ASIC chip is flip chip mounted to the at least one interposer chip (Deen Figs. 4-6 & ¶55-58).
CLAIM 22. Deen in view of Richard teaches the confinement apparatus package of claim 21, further comprising a backside cooler disposed on an exposed surface of the respective ASIC die, wherein the backside cooler is configured to cool the respective ASIC chip (Deen Figs. 4-6 & ¶55-58).
CLAIM 23. Deen in view of Richard teaches the confinement apparatus package of claim 17, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is in electrical communication with a third portion of the respective electrical channel disposed on the respective shunt capacitor chip via the at least one interposer chip (Deen Figs. 4-6 & ¶55-58).
CLAIM 24. Deen in view of Richard teaches the confinement apparatus package of claim 17, wherein a third portion of the respective electrical channel disposed on the respective shunt capacitor chip is in electrical communication with a second portion of the respective electrical channel disposed on the respective confinement apparatus die, at least in part, via at least one of (a) the respective interposer chip or (b) a through-silicon-via (TSV) formed in the respective confinement apparatus die (Deen Figs. 4-6 & ¶55-58).
CLAIM 25. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is in electrical communication with a second portion of the respective electrical channel disposed on the respective confinement apparatus die, at least in part, via a through silicon via (TSV) formed in the respective confinement apparatus die (Deen Figs. 4-6 & ¶55-58).
CLAIM 26. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein a first portion of the respective electrical channel disposed on the respective ASIC chip is configured to condition a voltage signal applied to one or more electrodes of the respective plurality of electrodes in electrical communication with the respective electrical channel (Deen Figs. 4-6 & ¶55-58).
CLAIM 27. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein the package substrate is at least one of a ceramic package or a printed circuit board (Deen Figs. 4-6 & ¶55-58 as modified by Richard – See regarding claim 1 teaching a package substate.).
CLAIM 28. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein a first portion of the respective electrical channel disposed on the respective ASIC die is in electrical communication a preliminary portion of the respective electrical channel disposed on the package substrate (Deen Figs. 4-6 & ¶55-58).
CLAIM 29. Deen in view of Richard teaches the confinement apparatus package of claim 14, wherein the confinement apparatus is a surface ion trap (Deen Figs. 4-6 & ¶55-58).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
9/14/2026
/JARRETT J STARK/ Primary Examiner, Art Unit 2898
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