DETAILED ACTION
This non-final action is responsive to the following communications:
Application filed on 09/18/2024.
Claims 1-20 are pending. Claims 1, 17, and 20 are independent.
Examiner Notes
A) Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification. B) Per MPEP 2173.04, Breadth of a claim is not to be equated with indefiniteness, but “If the claim is too broad because it reads on the prior art, a rejection under either 35 U.S.C. 102 or 103 would be appropriate”. C) Per MPEP 2173.04, undue breadth of the claim may be addressed under different statutory provisions, depending on the reasons for concluding that the claim is too broad. D) Examiner cites particular paragraphs or columns and lines in the references as applied to Applicant's claims for the convenience of the Applicant. Per MPEP 2141.02 VI prior art must be considered in its entirety. E) Per MPEP 2112 and 2112 V, express, implicit, and inherent disclosures of a prior art reference may be relied upon in the rejection of claims under 35 U.S.C. 102 or 103 and once a reference teaching product appearing to be substantially identical is made the basis of a rejection, and the examiner presents evidence or reasoning tending to show inherency, the burden of proof shifts to the applicant.
Notice of Pre-AIA or AIA Status
3. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
4. Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file. See ADS for priority date details.
Information Disclosure Statement
5. Acknowledgment is made of applicant's Information Disclosure Statement (IDS) filed on 09/18/2024. This IDS has been considered.
Drawings
6. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following claim language must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Regarding claim 17, “… a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units is greater than a length of the page buffer units in the first direction.” must be shown in the drawings, or cancelled from the claims. Drawings do not show this feature with at least relative dimensions, correlating features.
Regarding claim 20, “… a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units is smaller than a length of the page buffer units in the first direction.” must be shown in the drawings, or cancelled from the claims. Drawings do not show this feature with at least relative dimensions, correlations.
Corrected drawing sheets in compliance with 37 CFR 1.121 (d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121 (d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification Objections
7. The Title is objected to because the title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested:
“PAGE BUFFER and PERPHERAL CIRCUITRY LAYOUT METHOD IN A THREE-DIMENSIONAL MEMORY DEVICE”
Claim Rejections - 35 USC § 112
8. The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL. — The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
9a. Claim 17 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for “…memory device comprising: a first semiconductor layer comprising a peripheral circuit; and a second semiconductor layer on the first semiconductor layer along a third direction that is a vertical direction, the second semiconductor layer comprising a memory cell array, wherein the first semiconductor layer comprises a plurality of page buffer units extending in a first direction, the plurality of page buffer units being arranged in a second direction, wherein the second semiconductor layer comprises a plurality of bit lines electrically connected to the page buffer units and arranged at intervals along the first direction…”, does not reasonably provide enablement for “… a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units is greater than a length of the page buffer units in the first direction…”
The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. Fig. 10 in context of para [0137]-para [0142] where most relevant features are disclosed is pertinent for the analysis that follows. See e.g., para [0142] and Fig. 10 where it is taught that memory device 100A of the present disclosure, the value of 'S1 x (n-1)' corresponding to the length in the first direction X of the cell area CA may be greater than the value of 'S2 x (k-1)' corresponding to the length in the first direction X of the page buffer area PGBUF (distance between the bit lines adjacent to each other may be defined as a first pitch S1 and length in the first direction X of the high-voltage page buffer may be defined as a second pitch S2). While teaching such, spec fails to establish correlate between page buffer length and first pitch S1. On the contrary, it seems that the page buffer pitch S2 may be used in the limitation and being supported by spec. Similarly, Fig. 8A-Fig. 10, Fig. 16-Fig. 18 or relevant spec paragraphs para [0137]-para [0142], para [0175]-para [0177] fails to show features that establish the fact that a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units is greater than a length of the page buffer units in the first direction. It seems clear thus that the claimed limitations above highlighted do not find support in the teachings of the drawings/specification of the instant Application.
9b. Claim(s) 20 is/are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ),
first paragraph for substantially the same reasons as found in the rejection to claim 17.
9c. All dependent claims inclusive of claims 17-20 are rejected under this category for substantially the same reasons stated above.
For art rejection, the limitations will be interpreted according to claim description details.
Claim Rejections - 35 USC § 102
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
12. Claims 1-7, 10, and 13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by LIM et al. (US 2019/0164991 A1).
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Regarding independent claim 1, LIM teaches a memory device (Fig. 5A: 100 “memory device”. See Fig. 5A-Fig. 6, para [0061]) comprising:
a first semiconductor layer (Fig. 5A: L2 “semiconductor layer”) comprising a peripheral circuit (para [0064]: row decoder, page buffer); and
a second semiconductor layer (Fig. 5A: L1 “semiconductor layer”) on the first semiconductor layer (Fig. 5A: L2) in a vertical direction and comprising a memory cell array electrically connected to the peripheral circuit (Fig. 5A: vertically located above in the “3rd direction”),
wherein the first semiconductor layer (Fig. 5A: L2) comprises a page buffer area in which a page buffer circuit is disposed (Fig. 5A, Fig. 5B: 142, 144 “first- and second-page buffers”. See para [0064]),
wherein the second semiconductor layer (Fig. 5A: L1) comprises a cell area (Fig. 5C: 110 “memory cell array”. See also Fig. 5A) in which a plurality of bit lines (Fig. 5A: BL) is arranged at intervals along a first direction (Fig. 5A: “1st direction”), and
wherein a length of the page buffer area in the first direction (Fig. 6 x-sectional analysis shows this value approximately ~ 1/25 * array length 1st direction * 16) is different from a length of the cell area in the first direction (Fig. 6 x-sectional analysis shows this value approximately ~ array length 1st direction).
Regarding claim 2, LIM teaches the memory device of claim 1, wherein the length of the page buffer area in the first direction (Fig. 6 x-sectional analysis shows this value approximately ~ 1/25 * array length 1st direction * 16) is shorter than the length of the cell area in the first direction (Fig. 6 x-sectional analysis shows this value approximately ~ array length 1st direction).
Regarding claim 3, LIM teaches the memory device of claim 2, wherein the second semiconductor layer comprises a plurality of word lines extending in the first direction (Fig. 5A: WL extending in 1st direction) and electrically connected to the memory cell array (Fig. 5A: L1), wherein the first semiconductor layer (Fig. 5A: L2) comprises a decoder area in which a row decoder is disposed (Fig. 132, 134 “row decoder”), the row decoder being electrically connected to the word lines (para [0007]), and wherein the decoder area overlaps the cell area when viewed in a horizontal direction (See Fig. 5A: 132, 134 decoder area overlaps array area in L1).
Regarding claim 4, LIM teaches the memory device of claim 3, wherein the bit lines extend in a second direction and are arranged at intervals in the first direction (Fig. 5A: BL extend in 2nd direction), and wherein the page buffer circuit comprises a plurality of page buffer units arranged in the second direction (Fig. 5A: 142, 144 arranged in 2nd direction).
Regarding claim 5, LIM teaches the memory device of claim 4, wherein at least one of the bit lines does not overlap the page buffer area when viewed in the horizontal direction (Fig. 5A, Fig. 5B: bit lines in middle region do not overlap page buffers).
Regarding claim 6, LIM teaches the memory device of claim 4, wherein a number of the page buffer units arranged in the second direction (Fig. 5A: two) is different from a number of the bit lines that overlap the page buffer units (Fig. 5A: greater than two) when viewed in the horizontal direction among the bit lines (see Fig. 5A).
Regarding claim 7, LIM teaches the memory device of claim 2, wherein the second semiconductor layer further comprises a second metal line that extends in the first direction (Fig. 6: GSL line extend in 1st direction) and electrically connects a first bit line among the bit lines (Fig. 6: connected to BL towards center. See UPMs near center) and the page buffer circuit (Fig. 5A, Fig. 6: operably connected in a memory device), and
wherein the first bit line does not overlap the page buffer circuit (Fig. 6: connected to BL towards center do not overlap 144).
Regarding claim 10, LIM teaches the memory device of claim 2, wherein the first semiconductor layer further comprises a first metal line that extends in the first direction and electrically connects a first bit line among the bit lines and the page buffer circuit, and wherein the first bit line does not overlap the page buffer circuit. (See claim 7 rejection)
Regarding claim 13, LIM teaches the memory device of claim 10, wherein the second semiconductor layer (Fig. 6: L1) further comprises a through via (Fig. 6: MCP) that extends in the vertical direction with respect to the first semiconductor layer (Fig. 6: L1) and electrically connects the first bit line and the first metal line (para [0085]).
Lim-2379 (US 2020/0312379 A1).
13. Claims 17 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim-2379 (US 2020/0312379 A1).
Regarding independent claim 17, Lim-2379 teaches a memory device (Fi. 1: 100 memory device with features of Fig. 8, Fig. 12) comprising:
a first semiconductor layer (Fig. 8: 510, see also Fig. 12: 800) comprising a peripheral circuit (para [0090], with e.g., page buffers, row decoders. See also para [0124]); and
a second semiconductor layer on the first semiconductor layer along a third direction that is a vertical direction (Fig. 8 in context of para [0090]: memory cell array),
the second semiconductor layer comprising a memory cell array (para [0090], Fig. 8),
wherein the first semiconductor layer comprises a plurality of page buffer units extending in a first direction (Fig. 12: 840a1, 840a2, 840b1, 840b2 in context of para [0120], para [0121]),
the plurality of page buffer units (Fig. 12: 840a1, 840a2, 840b1, 840b2) being arranged in a second direction (Fig. 12: arrangement in 2nd direction),
wherein the second semiconductor layer comprises a plurality of bit lines (Fig. 8: BL1-BL4) electrically connected to the page buffer units (connected in the memory device) and arranged at intervals along the first direction (Fig. 8: 1st direction), and
wherein a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units (Fig. 12: base length 1st direction* 1/6 * 4) is greater than a length of the page buffer units in the first direction (Fig. 12: base length 1st direction * 2 * 1/6).
Regarding independent claim 20, Lim-2379 teaches a memory device (Fig. 5A: 100 “memory device”. See Fig. 5A-Fig. 6, para [0061]) comprising:
a first semiconductor layer (Fig. 5A: L2 “semiconductor layer”) comprising a peripheral circuit (para [0064]: row decoder, page buffer); and
a second semiconductor layer (Fig. 5A: L1 “semiconductor layer”) on the first semiconductor layer (Fig. 5A: L2) along a third direction that is a vertical direction (Fig. 5A: vertically located above in the “3rd direction”),
the second semiconductor layer comprising a memory cell array (Fig. 5C: 110 “memory cell array”. See also Fig. 5A),
wherein the first semiconductor layer (Fig. 5A: L2) comprises a plurality of page buffer units (Fig. 5A, Fig. 5B: 142, 144 “first- and second-page buffers”) extending in a first direction (Fig. 5A, Fig. 5B: “1st direction”. Para [0064]),
the plurality of page buffer units being arranged in a second direction (Fig. 5A, Fig. 5B: 142, 144 are arranged in “2nd direction” relative to each other),
wherein the second semiconductor layer (Fig. 5A, Fig. 5C: L1) comprising a plurality of bit lines (Fig. 5A: BL) electrically connected to the page buffer units (coupled in memory device) and arranged at intervals along the first direction (Fig. 5A: “1st direction”), and
wherein a value obtained by multiplying a pitch of the bit lines in the first direction by a number of the page buffer units (Fig. 6 x-sectional analysis shows this value approximately ~ 1/25 * array length 1st direction * 2) is smaller than a length of the page buffer units in the first direction (Fig. 6 x-sectional analysis shows this value approximately ~ 1/25 * array length 1st direction * 16).
Claim Rejections - 35 USC § 103
14. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
15. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
16. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or non-obviousness.
17. Claims 14, 15 is/are rejected under 35 U.S.C. 103 as being obvious over LIM et al. (US 2019/0164991 A1), in view of Lim-2379 (US 2020/0312379 A1).
Regarding claim 14, LIM teaches the memory device of claim 1. LIM is silent with respect to the details of length of the page buffer area being greater than the length of the cell area.
Lim-2379 teaches wherein the length of the page buffer area (Fig. 2: 240) in the first direction (larger in both 1st and 2nd direction) is greater than the length of the cell area (Fig. 2: Fig. 2: bit line area) in the first direction.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date to combine the teachings of Lim-2379 into the teachings of LIM such that larger page buffers can be employed in order to increase operating speed of device.
Regarding claim 15, LIM and Lim-2379 teach the memory device of claim 14. LIM teaches wherein the second semiconductor layer further comprises a step area in which ends of a plurality of word lines extending in the first direction are disposed (see Fig. 6 step area and WLs), and wherein at least a portion of the page buffer area overlaps the step area when viewed in the horizontal direction (Fig. 6: portion of the WL area overlaps with page buffer).
Allowable Subject Matter
Claims 8-9, 11-12, and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding the claims listed, the prior art of record does not appear to teach, suggest, or provide motivation for combination for the limitations described in details in the following:
Claims 8-9. The memory device of claim 7, wherein the first semiconductor layer comprises: a first bonding metal; a first metal line disposed under the first bonding metal and electrically connected to the page buffer circuit; and a first contact electrically connecting the first bonding metal and the first metal line, wherein the second semiconductor layer comprises: a second bonding metal corresponding to the first bonding metal; and a second contact electrically connecting the second metal line and the first bit line.
Claims 11-12. The memory device of claim 10, wherein the first semiconductor layer comprises: a first bonding metal; and a first contact electrically connecting the first bonding metal and the first metal line, the second semiconductor layer comprises: a second bonding metal corresponding to the first bonding metal; a second metal line disposed under the second bonding metal; a second contact electrically connecting the second metal line and the first bit line; and a third contact electrically connecting the second metal line and the second bonding metal, wherein the first bonding metal, the second bonding metal, the second metal line, and the first bit line overlap with each other when viewed in the horizontal direction.
Claim 16. The memory device of claim 15, wherein the first semiconductor layer comprises: a first bonding metal; and a first metal line disposed under the first bonding metal and electrically connected to the page buffer circuit, the second semiconductor layer comprises: a second bonding metal corresponding to the first bonding metal; and a second metal line disposed under the second bonding metal and electrically connected to a corresponding bit line among the bit lines, wherein the first bonding metal, the second bonding metal, and the first metal line overlap the step area when viewed in the horizontal direction.
Prior Art Not Relied Upon
The prior art made of record and not relied upon (MPEP § 707.05) is considered pertinent to applicant's disclosure: CHO (US 2023/0255036 A1): Fig. 1-Fig. 26B disclosure applicable for all claims. Kim (US 2006/0221739 A1): Kim teaches a memory device (para [0029]: “flash memory device” employing Fig. 3 circuitry) comprising: a memory block (e.g. Fig. 3: 100 connected to a flash memory block as understood by ordinary skill in the art); a first page buffer group (para [0036] and Fig. 3: PB1 to PB(2K-1)) and a second page buffer group (para [0049] and Fig. 3: PB2 to PB2K). CHOI (US 2018/0336949 A1): Fig. 1-Fig. 12 disclosure applicable for all claims.
It is suggested that applicant consider all prior arts made of record.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUSHFIQUE SIDDIQUE whose telephone number is (571)270-0424. The examiner can normally be reached on 7:00 am-4:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander George Sofocleous can be reached on (571) 272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MUSHFIQUE SIDDIQUE/Primary Examiner, Art Unit 2825
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