DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a 2nd NON-FINAL OFFICE ACTION in response to the amendment/ remarks filed 08/03/2026. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18889273 filed 09/18/2024 is a Continuation of 17738600, filed 05/06/2022, now U.S. Patent No. 12,119,071.
Response to Arguments
Applicant’s arguments, see amendment /remarks filed 08/03/2026, with respect to the rejection of claims 1-20 under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (Pub. No. US 20180102182), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Gaur et al. (PgPub. US 20220138066) Pub. Date: 2022-05-05, as set forth in the present office action.
The examiner agrees with Applicant’s arguments that Zhou does not disclose at least "an error instruction indicating a number of intentional errors" or "writing encoded data with the number of intentional errors indicated by the error instruction" recited in independent claim 1.
However, under a new ground(s) of rejection, Gaur discloses the above limitations, as described in the office action below.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Gaur et al. (PgPub. US 20220138066) Pub. Date: 2022-05-05.
Regarding independent Claims 1, 8 and 15, Gaur discloses a system and a method for injecting errors in a system-on-chip (SoC)., comprising:
a processing device coupled with a plurality of memory devices, FIG. 1 illustrates a system-on-chip (SoC) 100 that includes among others, a memory 102 associated with the processing core 110 “processing device” to execute a set of memory operations (such as read and write operations). The processing core 110 is further configured to transmit the control information CI to the injection logic circuit 106 for executing the set of memory operations.
receiving, an error instruction indicating a number of intentional errors for a memory device; [0026] The error injection controller 104 “host” may include suitable circuitry that is configured to perform one or more operations. The error injection controller 104 is coupled with the memory 102 by way of the injection logic circuit 106. Further, the error injection controller 104 is configured to generate error data ED, a trigger signal TS, and at least one of read and write access requests RAR and WAR associated with the memory 102. The error data ED is utilized to inject error in data that is written to or read from the memory 102.
writing, to the memory device, encoded data with the number of intentional errors indicated by the error instruction; [0072] At step 538, the injection logic circuit 106 injects the error in the second data SD to generate the erroneous second data ESD “intentional errors”. The injection logic circuit 106 injects the error in the second data SD after accessing the memory 102 based on the write access request WAR. At step 540, the injection logic circuit 106 transmits the erroneous second data ESD to the memory 102. At step 542, the memory 102 receives the erroneous second data ESD. At step 544, the memory 102 stores the erroneous second data ESD at the write address, thereby completing the write operation.
initiating a read command of the encoded data from the memory device;
[0073] Referring now to FIG. 5D, at step 546, the injection logic circuit 106 accesses the memory 102 based on the read access request RAR to execute the read operation. At step 548, the injection logic circuit 106 receives the first data FD from the error injection controller 104. At step 550, the injection logic circuit 106 transmits the first data FD to the memory 102. At step 552, the memory 102 receives the first data FD. At step 554, the memory 102 stores the first data FD at the read address.
[0074] At step 556, the injection logic circuit 106 receives the first data FD from the memory 102 for error injection. At step 558, the injection logic circuit 106 injects the error in the first data FD to generate the erroneous first data EFD.
determining, a number of detected errors using a result of the read command; [0075] Referring now to FIG. 5E, at step 562, the error detection circuit 112 receives at least one of the erroneous first data EFD and the erroneous second data ESD. At step 564, the error detection circuit 112 detects the error in at least one of the erroneous first data EFD and the erroneous second data ESD. The error detection circuit 112, based on the detection of the error, generates the error signal ES. At step 566, the error reporting circuit 114 receives the error signal ES from the error detection circuit 112.
generating an error check functionality indicator using the number of detected errors; sending, to the host, the error check functionality indicator.
[0076] At step 568, the error reporting circuit 114 identifies, based on the error signal ES, at least one of single-bit and multi-bit errors as the detected error. At step 570, the error reporting circuit 114 corrects the single-bit error. At step 572, the error reporting circuit 114 resets the SoC 100 when the multi-bit error is identified.
Regarding Claims 2, 9, 16, Gaur discloses sending a dedicated read command to read the encoded data from the verification portion. [0030] When the injection logic circuit 106 receives the read access request RAR, the injection logic circuit 106 is configured to transmit the read access request RAR to the memory 102, and access the memory 102 to read the first data FD at the read address from the memory 102 (i.e., receive the first data FD from the memory 102). Further, the injection logic circuit 106 injects the error in the first data FD, based on the error data ED and the trigger signal TS, to generate the erroneous first data EFD.
Regarding Claims 3-5, 10-12, 17, 18, Gaur discloses wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors, wherein the error check functionality request includes the dummy pattern and the number of intentional errors. [0031] The data generator 108 is coupled with the injection logic circuit 106, and configured to receive the input data ID from the injection logic circuit 106 and generate the second data SD. In one embodiment, the data generator 108 generates the second data SD by combining the input data ID with the ECC bits. In another embodiment, the data generator 108 generates the second data SD by combining the input data ID with parity bits. The data generator 108 is further configured to transmit the second data SD to the injection logic circuit 106.
[0030 When the injection logic circuit 106 receives the write access request WAR, the injection logic circuit 106 injects the error in the second data SD, based on the error data ED and the trigger signal TS, to generate the erroneous second data ESD. Further, the injection logic circuit 106 is configured to transmit the write access request WAR to the memory 102, and access the memory 102 to write the erroneous second data ESD at the write address in the memory 102 (i.e., transmit the erroneous second data ESD to the memory 102).
Regarding Claims 6, 13, 19, Gaur discloses wherein the error check functionality indicator comprises an error correction interrupt signal. [0037] The error reporter is coupled with the error detection circuit 112, and configured to receive the error signal ES from the error detection circuit 112 and identify, based on the error signal ES, at least one of the single-bit and multi-bit errors as the detected error. In one embodiment, the error reporter is further configured to correct the single-bit error indicated by the error signal ES, and generate a reporting signal (not shown) when the error signal ES indicates the multi-bit error (i.e., the two-bit error and the three-bit error).
Regarding Claims 7, 14, 20, Gaur discloses wherein the number of intentional errors comprise one or two errors. [0026] Further, the error injection controller 104 is configured to generate error data ED “intentional errors”, a trigger signal TS, and at least one of read and write access requests RAR and WAR associated with the memory 102. The error data ED is utilized to inject error in data that is written to or read from the memory 102. The trigger signal TS is indicative of initiating error injection in the data that is written to or read from the memory 102.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,119,071. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,119,071, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Double Patenting Table A.
18889273 Instant Application Claims
(U.S. Patent No. 12,119,071) Claims
Independent 1. A method comprising:
receiving, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
writing, to the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiating a read command of the encoded data from the memory device;
determining, a number of detected errors using a result of the read command;
generating an error check functionality indicator using the number of detected errors; and
sending, to the host, the error check functionality indicator.
1. A method comprising:
receiving, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
writing, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiating a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request;
determining, a number of detected errors using a result of the read command;
generating an error check functionality indicator using the number of detected errors; and
sending, to the host, the error check functionality indicator.
Independent 8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the encoded data from the memory device;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
Independent 15. A system comprising:
a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to the memory device, encoded data with the number of intentional errors indicated by the error instruction, wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors;
initiate a read command of the encoded data from the memory device;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
15. A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to: receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request and wherein the verification portion comprises a portion of memory not accessible using standard read commands;
determine, a number of detected errors using based on a result of the read command and a number of intentional errors in the encoded data, an error check functionality indicator;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator corresponding to the number intentional errors in the encoded data.
Claims 2, 9, 16, wherein the encoded data is written to a verification portion of the memory device that is not accessible using standard read commands.
Claims 2, 9, wherein the verification portion of memory comprises a portion of memory not accessible using standard read commands.
Claims 3-5, 10-12, 17, 18, wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors, wherein the error check functionality request includes the dummy pattern and the number of intentional errors and wherein receiving the error check functionality request including the dummy pattern causes the writing of the encoded dummy pattern, wherein the writing of the encoded dummy pattern occurs prior to the receiving of the error check functionality request.
Claims 3, 4, 10, 11, 16, 17, generating the encoded data by encoding a dummy pattern using an error correcting code.
wherein the error check functionality request further includes the dummy pattern and wherein receiving the error check functionality request including the dummy pattern causes the writing, to the verification portion, the encoded data.
Claims 6, 13, 19, wherein the error check functionality indicator comprises an error correction interrupt signal.
Claims 5, 18, wherein the error check functionality indicator comprises an error correction interrupt signal.
Claims 7, 14, 20, wherein the number of intentional errors comprise one or two errors.
Claims 6, 13, 19, wherein the number of intentional errors comprises one or two errors.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: August 18, 2026
Non-Final Rejection 20260423
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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