DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the present Application filed 09/18/2024. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continuity/ Priority Information
The present Application 18889273 filed 09/18/2024 is a Continuation of 17738600, filed 05/06/2022, now U.S. Patent No. 12,119,071.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/20/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 9 and 16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 2, 9, 16, recite a negative limitation “a verification portion of the memory device that is not accessible using standard read commands”, which render the Claims indefinite, i.e. due to the inclusion of expression “not accessible”. It is not clear how one of ordinary skill in the art is unable to access a memory device using standard read commands. The limitations as recited, tend to define the invention in terms of what it is not, rather than pointing out the invention. Any negative limitation or exclusionary proviso must have basis in the original disclosure. In this case, there is no sufficient description in the specification for the negative limitation. However, the specification describes in para. [0038] error check function verifier 113 accesses verification portion 215 by enabling a special interface and sending a dedicated read command. For example, error check function verifier 113 may use an Extensible Firmware Interface (EFI) command or another command with similar timing as a standard read command that provides restricted access to verification portion 215.
Applicant should recite limitations from the specification into the Claims “by enabling a special interface and sending a dedicated read command” to access the verification portion.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zhou (Pub. No. US 20180102182) Pub. Date: 2018-04-12.
Regarding independent Claims 1, 8 and 15, Zhou discloses methods and apparatuses for testing a storage unit, comprising:
A system comprising a plurality of memory devices, and a processing device, operatively coupled with the plurality of memory devices, [0024] FIG. 1 is the system architecture 10 of the flash memory contains a processing unit 110. The system architecture 10 uses several electrical signals for coordinating commands and data transfer between the processing unit 110 and the storage unit 180, including data lines, a clock signal and control lines.
receiving, from a host, an error check functionality request for a memory device, that includes an error instruction indicating a number of intentional errors; [0029] FIG. 8 is a flowchart illustrating a method for testing a storage unit. After receiving a test write command from the host device 160 through the access interface 150 (step S810), the processing unit 110 issues a control signal CTRL to direct the data dispatcher 120 to send data DAT1 (including a PBA) from the host device 160 to the test writer 131 (step S820).
writing, to the memory device, encoded data with the number of intentional errors indicated by the error instruction; and initiating a read command of the encoded data from the memory device;
The processing unit 110 issues a command CMD2 to direct the access interface 170 to read one or more test patterns DAT2 from the test writer 131 and program the test pattern(s) DAT2 into a designated PBA of the storage unit 180 (step S830), and next, issues a command CMD3 to direct the access interface 170 to read test pattern(s) DAT3 from the designated PBA and output the test pattern(s) DAT3 to the test reader 133 (step S840).
determining, a number of detected errors using a result of the read command; generating an error check functionality indicator using the number of detected errors; [0028] FIG. 6 is a block diagram of a test reader. FIG. 7A is a schematic diagram of a test data read by an ECC decoder. An ECC decoder 610 uses the ECC 770 to determine whether the scrambled data 710, the metadata 730 and the parity 750 have any errors. When the errors have not been fixed successfully, the ECC decoder 610 transmits a message RT1 to the processing unit 110 to indicate that the test data DAT3 contains un-recoverable errors.
When an error has been detected, “detected errors” the CRC decoder 650 transmits a message RT2 to the processing unit 110 to indicate that the test data DAT3 hasn't passed the CRC examination. The processing unit 110 generates an integrated message RT according to the messages RT1 and RT2 and replies the integrated message RT to the host device 160. In one example, the message RT indicates that the programming of test data into the designated PBA is successful or has failed. In another example, the message RT indicates that test data being programmed into the designated PBA has passed the ECC and CRC examination.
sending, to the host, the error check functionality indicator. FIG. 8. The processing unit 110 receives a test result RT′ from the test reader 133 (step S850), generates a test message RT according to the test result RT′ and replies with the test message RT to the host device 160 (step S860).
Regarding Claims 2, 9, 16, Zhou discloses wherein the encoded data is written to a verification portion of the memory device that is not accessible using standard read commands. When a write command CMD1 issued by the host device 160 instructs a test write, the processing unit 110 enters the test write mode. Specifically, in the test write mode, the processing unit 110 issues a control signal CTRL to direct the data dispatcher 120 to send data DAT1 to a test writer 131. The test writer 131 generates test patterns DAT2 according to the data DAT1 and dummy data output from a dummy-data generator 140. Next, the processing unit 110 issues a command CMD2 to direct the access interface 170 to read one or more test patterns DAT2 from the test writer 131 and program the test pattern(s) DAT2 into a designated PBA (physical block address) of the storage unit 180.
Regarding Claims 3-5, 10-12, 17, 18, Zhou discloses wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors, wherein the error check functionality request includes the dummy pattern and the number of intentional errors and wherein receiving the error check functionality request including the dummy pattern causes the writing of the encoded dummy pattern, wherein the writing of the encoded dummy pattern occurs prior to the receiving of the error check functionality request. [0027] FIG. 4 is a block diagram illustrating a test writer. A test writer 131 contains a CRC (Cyclic Redundancy Check) encoder 410, a scrambler 430 and an ECC (Error-Correcting Code) encoder 450. The CRC encoder 410 may receive metadata DAT1 through the data dispatcher 120 and receive dummy data DUM from the dummy-data generator 140. The CRC encoder 410 encodes the dummy data DUM and the metadata DAT1 by adding a fixed-length parity for the purpose of error detection and outputs a result DAT1′ to the scrambler 430.
Regarding Claims 6, 13, 19, Zhou discloses wherein the error check functionality indicator comprises an error correction interrupt signal.
[0028] FIG. 6 When the errors have not been fixed successfully, the ECC decoder 610 transmits a message RT1 “interrupt signal” to the processing unit 110 to indicate that the test data DAT3 contains un-recoverable errors. The processing unit 110 generates an integrated message RT according to the messages RT1 and RT2 and replies the integrated message RT to the host device 160.
Regarding Claims 7, 14, 20, Zhou discloses wherein the number of intentional errors comprise one or two errors. [0026] The test reader 133 verifies each bit of the test pattern(s) DAT3 for determining whether the read data DAT3 is correct or has error bit(s) and outputs a test result RT′ to the processing unit 110. The processing unit 110 replies a test result RT to the host device 160 via the access interface 150.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 1-20 of U.S. Patent No. 12,119,071. Although the claims at issue are not identical, they are not patentably distinct from each other because the Claims of the instant Application are broader in scope than the Claims recited in the U.S. Patent No. 12,119,071, and thus anticipate the Claims of the instant Application. Claims of the instant application therefore are not patently distinct from the earlier patent claims and as such are unpatentable over obvious-type double patenting. A later patent/application claim is not patentably distinct from an earlier claim if the later claim is anticipated by the earlier claim.
“A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over, or anticipated by, the earlier claim. In re Longi, 759 F.2d at 896,225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Berg, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of bviousness- type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus).“ ELI LILLY AND COMPANY v BARR LABORATORIES, INC., United States Court of Appeals for the Federal Circuit, ON PETITION FOR REHEARING EN BANC (DECIDED: May 30, 2001).
Double Patenting Table A.
18889273 Instant Application Claims
(U.S. Patent No. 12,119,071) Claims
Independent 1. A method comprising:
receiving, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
writing, to the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiating a read command of the encoded data from the memory device;
determining, a number of detected errors using a result of the read command;
generating an error check functionality indicator using the number of detected errors; and
sending, to the host, the error check functionality indicator.
1. A method comprising:
receiving, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
writing, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiating a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request;
determining, a number of detected errors using a result of the read command;
generating an error check functionality indicator using the number of detected errors; and
sending, to the host, the error check functionality indicator.
Independent 8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the encoded data from the memory device;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
8. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
Independent 15. A system comprising:
a plurality of memory devices; and a processing device, operatively coupled with the plurality of memory devices, to:
receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to the memory device, encoded data with the number of intentional errors indicated by the error instruction, wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors;
initiate a read command of the encoded data from the memory device;
determine, a number of detected errors using a result of the read command;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator.
15. A system comprising:
a plurality of memory devices; and
a processing device, operatively coupled with the plurality of memory devices, to: receive, from a host, an error check functionality request for a memory device, wherein the error check functionality request includes an error instruction indicating a number of intentional errors;
write, to a verification portion of the memory device, encoded data with the number of intentional errors indicated by the error instruction;
initiate a read command of the verification portion, wherein the verification portion of the memory device is readable in response to the error check functionality request and wherein the verification portion comprises a portion of memory not accessible using standard read commands;
determine, a number of detected errors using based on a result of the read command and a number of intentional errors in the encoded data, an error check functionality indicator;
generate an error check functionality indicator using the number of detected errors; and
send, to the host, the error check functionality indicator corresponding to the number intentional errors in the encoded data.
Claims 2, 9, 16, wherein the encoded data is written to a verification portion of the memory device that is not accessible using standard read commands.
Claims 2, 9, wherein the verification portion of memory comprises a portion of memory not accessible using standard read commands.
Claims 3-5, 10-12, 17, 18, wherein the encoded data is an encoded dummy pattern based on a dummy pattern, an error correcting code, and the number of intentional errors, wherein the error check functionality request includes the dummy pattern and the number of intentional errors and wherein receiving the error check functionality request including the dummy pattern causes the writing of the encoded dummy pattern, wherein the writing of the encoded dummy pattern occurs prior to the receiving of the error check functionality request.
Claims 3, 4, 10, 11, 16, 17, generating the encoded data by encoding a dummy pattern using an error correcting code.
wherein the error check functionality request further includes the dummy pattern and wherein receiving the error check functionality request including the dummy pattern causes the writing, to the verification portion, the encoded data.
Claims 6, 13, 19, wherein the error check functionality indicator comprises an error correction interrupt signal.
Claims 5, 18, wherein the error check functionality indicator comprises an error correction interrupt signal.
Claims 7, 14, 20, wherein the number of intentional errors comprise one or two errors.
Claims 6, 13, 19, wherein the number of intentional errors comprises one or two errors.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20250370860 JEONG; Young Mok et al. [0071] The severe error detection circuit 410 may monitor an error check operation of a row corresponding to the scrub row address RADD_E according to the scrub command ECS, the scrub active signal ACT_E, the scrub read signal RD_E, and the scrub write signal WT_E. During the error check operation, the severe error detection circuit 410 may output a detection signal SEV_SUM by detecting whether a severe error has occurred in a row corresponding to the scrub row address RADD_E based on the fourth to sixth local error signals ERR_67, ERR_E, and ERR_89.
US 20220413713 CHOI; Joon Yong [0031] The error correction circuit 261 may correct an error in data DATA′ that is read from the memory core based on an error correction code ECC that is read from the memory core 280 during a read operation. Herein, correcting the error may mean detecting an error in the data DATA′ and, when an error is detected, correcting the error in the data DATA′. The error correction circuit 261 may detect and correct an error in the error correction code ECC together with the data DATA′.
US 20220121518 Chung; Hoi-Ju et al. [0142] Referring to FIGS. 10, 12 and 14,The second sub unit of data 513 includes an error bit ER. The ECC decoder 430 performs an ECC decoding on the first unit of codeword CW to detect the bit error ER, corrects the detected bit error ER in the second sub unit of data 513 to generate a corrected second sub unit of data 513′ and provides the corrected second sub unit of data 513′ to the I/O gating circuit 290 as a reference numeral indicates 522.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: April 29, 2026
Non-Final Rejection 20260423
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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