DETAILED ACTION
Priority Claim
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
IDS
All references provided in the IDS dated 09/19/2024, 04/29/2025, and 05/08/2026 have been considered.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1, 5, 6 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding Independent Claim 1,
Claim 1, lines 1-2 recite: “a thin film transistor provided over a substrate, comprising a metal oxide layer over the substrate”. It is unclear how the thin film transistor is provided over a substrate but also includes it. It has been interpreted to mean “a thin film transistor, comprising: a metal oxide layer over a substrate”. Appropriate correction is required. Claims 2-16 are rejected by virtue of their dependency on Claim 1.
Claim 1, line 3 recites: “having crystallinity in contact with the metal oxide layer”. It is unclear how crystallinity can be in contact with the metal oxide layer. It has been interpreted to mean an oxide semiconductor layer in contact with the metal oxide layer. Appropriate correction is required. Claims 2-16 are rejected by virtue of their dependency on Claim 1.
Claim 1, lines 9-10 recites: “each of the plurality of crystal grains comprising at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>”. Is it unclear if the plurality of crystal grains each requires the one each of the <001>, <101> and <111>, or at minimum just requires one of the three orientations. It has been interpreted to mean a minimum of one of the crystal orientations <001>, <101>, <111>. Appropriate correction is required. Claims 2-16 are rejected by virtue of their dependency on Claim 1. Regarding Dependent Claim 5,
Claim 5, lines 1-2 recites: “wherein at least one of the plurality crystal grains comprises at least two of the crystal orientation comprises…”. It is unclear how one of the crystal grains can have multiple crystal orientations. It has been interpreted to mean the plurality of crystal grains have at least two different types of crystal grains from the list <001>, <101> and <111>. Appropriate correction is required.
Regarding Dependent Claim 6,
Claim 6, line 1 recites: “an average GOS”. “GOS” is not descriptive. In view of the specification, it has been interpreted to mean “grain orientation spread”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2, 5, 9, 10, 12-16 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1).
Re: Independent Claim 1, Ishihara discloses:
A thin film transistor (Ishihara, transistor; Fig. 1B, element 200) provided over a substrate (Ishihara, substrate; Fig. 1B, element 100), comprising:
a metal oxide layer (Ishihara, metal oxide layer; Fig. 1B, element 108) over the substrate;
an oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) having crystallinity (Ishihara, 106 may have a non-single crystal structure, or a polycrystalline structure... ¶ [0096]) in contact with the metal oxide layer (Ishihara, ¶ [0098]);
a gate electrode (Ishihara, gate electrode layer; Fig. 1B, element 102) overlapping the oxide semiconductor layer (Ishihara, Fig. 1B shows 102 and 106 overlapping in plan view); and
an insulating layer (Ishihara, gate insulating layer; Fig. 1B, element 104) between the oxide semiconductor layer and the gate electrode (Ishihara, Fig. 1B shows 104 between 102 and 106),
wherein the oxide semiconductor layer comprises a plurality of crystal grains (Ishihara, ¶ [0096] discloses a polycrystalline structure, which is a plurality of crystal grains),
Ishihara is silent regarding:
wherein the oxide semiconductor layer comprises a plurality of crystal grains, each of the plurality of crystal grains comprising at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>
Lee discloses:
wherein the oxide semiconductor layer (Lee, dielectric layer, Fig. 1, element 420, ¶ [0063]) comprises a plurality of crystal grains (Lee. Fig. 1B, ¶ [0063 - 0064]), each of the plurality of crystal grains comprising at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111> (Lee, ¶ [0064]),
Ishihara discloses a thin film transistor comprising a substrate, a metal oxide layer, an oxide semiconductor layer with crystallinity, a gate electrode, an insulating layer, and the oxide semiconductor layer being polycrystalline (i.e. comprising a plurality of grains). Ishihara does not explicitly disclose that the plurality of grains includes at least one of east one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>. Lee discloses an oxide semiconductor layer comprising a plurality of grains, which includes at least one of a crystal orientation <001>, a crystal orientation <101>, and a crystal orientation <111>. Both disclose oxide semiconductor layers and are therefore analogous art. In the absence of any criticality or unexpected results, it would be obvious to a person of ordinary skill in the art (POSITA) before the effective filing date to include the oxide semiconductor layer, as disclosed by Lee, to the invention of Ishihara, for the benefit of influencing some optical properties, such as the refractive index and other light absorption properties.
Furthermore, Ishihara and Lee disclose the thin film transistor device comprising a substrate, a metal oxide layer, an oxide layer with crystallinity, a gate electrode, and an insulating layer, and wherein the semiconductor layer comprises a plurality of crystal grains, but does not disclose the limitation "obtained by an electron backscatter diffraction (EBSD) method, and wherein in occupancy rates of crystal orientations calculated based on measurement points having crystal orientations with a crystal orientation difference greater than or equal to 0 degrees and less than or equal to 15 degrees with respect to a normal direction of a surface of the substrate,", which is a product-by-process limitation. The recited limitation does not impart structure or function to the thin film transistor that distinguishes it from the thin film transistor, as disclosed by Ishihara, as modified by Lee. The patentability of the thin film transistor device is determined by the product, rather than the particular method by which the oxide semiconductor layer is deposited (see MPEP § 2113).
Ishihara, as modified by Lee, discloses:
the proportion of the crystal grains grown in the dielectric layer in a direction close to the <hk0>, <h00>, and/or <0k0> direction may be about 10% or more (for example, 20% or more, 30% or more, 40% or more, and/or 50% or more) (Lee, ¶ [0064]).
but does not explicitly disclose:
an occupancy rate of the crystal orientation <001> is less than or equal to 5%.
In the absence of any criticality or unexpected results, it would be obvious to a POSITA to select a configuration from the disclosed variable configurations, such that the <110> (analogous to <101>) has a proportion of 50% or more (i.e. 95%), such that the proportion of <100> (analogous to <001>) is 5% or less, arriving at the invention as claimed, as a matter of routine optimization, yielding predictable results of controlling grain proportions, with the known benefit of tuning optical parameters.
Re: Dependent Claim 2, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein an occupancy rate of the crystal orientation <101> (Lee, ¶ [0064], occupancy rate is 95%) is greater than or equal to 4 times the occupancy rate of the crystal orientation <001> (Lee, ¶ [0064, occupancy rate is 5%, which puts the occupancy rate of <101> crystals at greater than or equal to 4 times the occupancy rate of <001>).
Re: Dependent Claim 5, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein at least one of the plurality of crystal grains (Lee, crystal grains, Fig. 1, shown within element 420, ¶ [0064]) comprises at least two of the crystal orientation <001>, the crystal orientation <101>, and the crystal orientation <111> (Lee, Fig. 1, shows the <001> and <110>, which is at least two of the crystal orientations).
Re: Dependent Claim 9, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) comprises indium and at least one or more metal elements (Ishihara, ¶ [0083], "The oxide semiconductor layer 106 is typically formed using an In--Ga oxide, an In--Zn oxide, or an In-M-Zn oxide (M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf)", and
wherein a ratio of the indium to all metal elements including the indium in the oxide semiconductor layer is greater than or equal to 50% (Ishihara, ¶ [0084], discloses a ratio of In:M:Zn=3:1:2, which is greater than or equal to 50%).
Re: Dependent Claim 10, Ishihara and Lee disclose all the limitations of claim 9 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the metal oxide layer (Ishihara, metal oxide layer; Fig. 1B, element 108) comprises one of the at least one or more metal elements (Ishihara, ¶ [0063]).
Re: Dependent Claim 12, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) is deposited (Ishihara, ¶ [0143])
Ishihara, as modified by Lee, does not explicitly disclose:
wherein the oxide semiconductor layer is deposited while a substrate temperature lower than or equal to 50°C is controlled during deposition.
Ishihara, as modified by Lee, discloses the oxide semiconductor layer is deposited. The limitation "is deposited while a substrate temperature lower than or equal to 50°C is controlled during deposition." is a product-by-process limitation. The recited limitation does not impart structure or function to the oxide semiconductor layer that distinguishes it from the oxide semiconductor layer, as disclosed by Ishihara. The patentability of the thin film transistor device is determined by the product, rather than the particular method by which the oxide semiconductor layer is deposited (see MPEP § 2113).
Re: Dependent Claim 13, Ishihara and Lee disclose all the limitations of claim 12 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) is deposited (Ishihara, ¶ [0143]), oxygen (Ishihara, ¶ [0150 - 0152])
Ishihara, as modified by Lee, does not explicitly disclose:
wherein the oxide semiconductor layer is deposited under an oxygen partial pressure less than or equal to 10%.
Ishihara, as modified by Lee, discloses the oxide semiconductor layer is deposited and also discloses the use of oxygen. The limitation "is deposited under an oxygen partial pressure less than or equal to 10%." is a product-by-process limitation. The recited limitation does not impart structure or function to the oxide semiconductor layer that distinguishes it from the oxide semiconductor layer, as disclosed by Ishihara. The patentability of the thin film transistor device is determined by the product, rather than the particular method by which the oxide semiconductor layer is deposited (see MPEP § 2113).
Re: Dependent Claim 14, Ishihara and Lee disclose all the limitations of claim 13 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) is crystallized (Ishihara, 106 may have a non-single crystal structure, or a polycrystalline structure... ¶ [0096]) is crystallized by annealing after deposition (Ishihara, ¶ [0150 - 0152]).
Ishihara, as modified by Lee, discloses the oxide semiconductor layer is crystallized (as deposited) but also that heat treatment (annealing) may be performed after the layer is deposited. The limitation "is crystallized by annealing after deposition." is a product-by-process limitation. The recited limitation does not impart structure or function to the oxide semiconductor layer that distinguishes it from the oxide semiconductor layer, as disclosed by Ishihara. The patentability of the thin film transistor device is determined by the product, rather than the particular method by which the oxide semiconductor layer is deposited (see MPEP § 2113).
Re: Dependent Claim 15, Ishihara and Lee disclose all the limitations of claim 14 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the oxide semiconductor layer (Ishihara, oxide semiconductor layer; Fig. 1B, element 106) is annealed (Ishihara, heat treatment, ¶[ 0150]) at a reaching temperature higher than or equal to 350°C and lower than or equal to 450°C (Ishihara, ¶ [0150]).
While Ishihara, as modified by Lee, discloses wherein the oxide semiconductor layer is annealed at temperatures lower than or equal to 450°C, the limitation "is annealed at a reaching temperature higher than or equal to 350°C and lower than or equal to 450°C." is a product-by-process limitation. The recited limitation does not impart structure or function to the oxide semiconductor layer that distinguishes it from the oxide semiconductor layer, as disclosed by Ishihara. The patentability of the thin film transistor device is determined by the product, rather than the particular method by which the oxide semiconductor layer is deposited (see MPEP § 2113).
Re: Dependent Claim 16, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
An electronic device comprising the thin film transistor according to claim 1 (Ishihara, semiconductor device; Fig. 7B, element 310).
Claim(s) 3-4 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1) and in further view of Yu (US 9493357 B2).
Re: Dependent Claim 3, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
the occupancy rate of the crystal orientation <001> (Lee, ¶ [0064], occupancy rate is 5%)
Ishihara, as modified by Lee, does not explicitly disclose:
wherein an occupancy rate of the crystal orientation <111> is greater than or equal to 4 times the occupancy rate of the crystal orientation <001>.
Yu discloses:
<111> grains (Yu, Cols. 1-2, lines 65 – 29)
Ishihara, as modified by Lee, discloses the occupancy rate of the crystal orientation <101>, and discloses this may be variable, but does not explicitly disclose an occupancy rate of <111> grains, such that a ratio of an occupancy rate of the crystal orientation <101> to an occupancy rate of the crystal orientation <111> is greater than or equal to 0.7 and less than or equal to 1.5 . Yu discloses <111> grains and discloses a technique to impede growth of crystals having other orientations/grow select orientations. Both disclose crystal orientations and are therefore analogous art. In the absence of criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to include <111> grains, as disclosed by Yu, in the invention by Ishihara, as modified by Lee, and it would be further obvious to a POSITA to modify the proportions of the occupancy rates of the <111> and <101> crystal orientations, as disclosed by Yu, arriving at the invention as claimed, as a matter of routine optimization, yielding predictable results of controlling grain proportions, with the known benefit of tuning optical parameters.
Re: Dependent Claim 4, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein a ratio of an occupancy rate of the crystal orientation <101> (Lee, the proportion of the crystal grains grown in the dielectric layer in a direction close to the <hk0>, <h00>, and/or <0k0> direction may be about 10% or more (for example, 20% or more, 30% or more, 40% or more, and/or 50% or more, ¶ [0064], i.e. occupancy rate of crystal orientation <101>)
Ishihara, as modified by Lee, does not explicitly disclose:
wherein a ratio of an occupancy rate of the crystal orientation <101> to an occupancy rate of the crystal orientation <111> is greater than or equal to 0.7 and less than or equal to 1.5.
Yu discloses:
<111> grains (Yu, Cols. 1-2, lines 65 - 29)
Ishihara, as modified by Lee, discloses the occupancy rate of the crystal orientation <101>, and discloses this may be variable, but does not explicitly disclose an occupancy rate of <111> grains, such that a ratio of an occupancy rate of the crystal orientation <101> to an occupancy rate of the crystal orientation <111> is greater than or equal to 0.7 and less than or equal to 1.5 . Yu discloses <111> grains and discloses a technique to impede growth of crystals having other orientations/grow select orientations. Both disclose crystal orientations and are therefore analogous art. In the absence of criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to include <111> grains, as disclosed by Yu, in the invention by Ishihara, as modified by Lee, and it would be further obvious to a POSITA to modify the proportions of the occupancy rates of the <111> and <101> crystal orientations, arriving at the invention as claimed, as a matter of routine optimization, yielding predictable results of controlling grain proportions, with the known benefit of tuning optical parameters.
Claim(s) 6 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1) and in further view of Tarutani (US 20200181788 A1).
Re: Dependent Claim 6, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
the plurality of crystal grains (Ishihara, ¶ [0096] discloses a polycrystalline structure, which is a plurality of crystal grains)
Ishihara, as modified by Lee, does not explicitly disclose:
wherein an average GOS of the plurality of crystal grains is greater than or equal to 5 degrees.
Tarutani discloses:
wherein an average GOS of the plurality of crystal grains is greater than or equal to 5 degrees (Tarutani, ¶ [0021], discloses 2.5° or more, and a method of calculating GOS, expression 1, after ¶ [0023]).
Ishihara, as modified by Lee, discloses a plurality of crystal grains but does not explicitly disclose an average grain orientation spread of the plurality of crystal grains is greater than or equal to 5 degrees. Tarutani discloses that an average GOS has a value of 2.5° or more, but also discloses a method of calculating GOS. In the absence of any criticality or unexpected results, it would be obvious to a POSITA before the effective filing date to use the method of calculating the average GOS, to obtain an average GOS of the plurality of crystal grains to be greater than 5 degrees, as disclosed by Tarutani, in the invention disclosed by Ishihara, as modified by Lee, as a matter of routine optimization, such as increasing or decreasing the number of measurements, arriving at the invention as claimed, for the known benefit of improving stress and defects within the device.
Claim(s) 7 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1) and in further view of Takebe (US 20190226073 A1).
Re: Dependent Claim 7, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
plurality of crystal grains (Ishihara, ¶ [0096] discloses a polycrystalline structure, which is a plurality of crystal grains)
Ishihara, as modified by Lee, does not explicitly disclose:
average crystal grain size of the plurality of crystal grains is greater than or equal to 1 μm.
Takebe discloses:
average crystal grain size of the plurality of crystal grains is greater than or equal to 1 μm (Takebe, ¶ [0036], discloses "the average grain size dave (μm) is set at 2.5 μm or more").
Ishihara, as modified by Lee, discloses a plurality of crystal grains, but does not explicitly disclose the average grain size to be greater than or equal to 1 μm. Takebe discloses the average grain size to be greater than or equal to 1 μm in a thin titanium sheet. All references disclose use of crystal grains and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to ensure that the average crystal grain size of the plurality of crystal grains is greater than or equal to 1 μm, which can be controlled by steps such as annealing (Takebe, ¶ [0052]), as disclosed by Takebe, for the benefit of a more stable production (Takebe, ¶ [0036]).
Claim(s) 8 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1) and in further view of Nakayama (US 20210155550 A1).
Re: Dependent Claim 8, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
plurality of crystal grains (Ishihara, ¶ [0096] discloses a polycrystalline structure, which is a plurality of crystal grains)
Ishihara, as modified by Lee, does not explicitly disclose:
wherein a maximum crystal grain size of the plurality of crystal grains is greater than or equal to 2 μm.
Nakayama discloses:
wherein a maximum crystal grain size of the plurality of crystal grains is greater than or equal to 2 μm (Nakayama, silicon nitride grains; Fig. 2, element 3, ¶ [0077], "silicon nitride grains having a maximum grain size of 7 μm or greater").
Ishihara, as modified by Lee, discloses a plurality of crystal grains, but does not explicitly disclose wherein a maximum crystal grain size of the plurality of crystal grains is greater than or equal to 2 μm. Nakayama discloses silicon nitride grains having a maximum grain size of 7 μm or greater ¶ [0077]. All references disclose use of crystal grains and are therefore analogous art. It would be obvious to a POSITA before the effective filing gate to select a maximum crystal grain size greater than or equal to 2 μm, as disclosed by Nakayama, for the benefit of decreased lattice distortion.
Claim(s) 11 is rejected under AIA 35 U.S.C. 103 as being unpatentable over Ishihara (US 20150084043 A1) in view of Lee (US 20220254870 A1) and in further view of Yabe (US 9552981 B2).
Re: Dependent Claim 11, Ishihara and Lee disclose all the limitations of claim 1 on which this claim depends. Ishihara, as modified by Lee, further discloses:
wherein the metal oxide layer (Ishihara, metal oxide layer; Fig. 1B, element 108)
Ishihara, as modified by Lee, does not explicitly disclose:
wherein the metal oxide layer comprises aluminum oxide.
Yabe discloses:
wherein the metal oxide layer comprises aluminum oxide (Yabe, aluminum oxide film; Fig. 2L, element 4, Col. 4, lines 15-21).
Ishihara, as modified by Lee, discloses a metal oxide layer but does not disclose this metal oxide layer to comprise aluminum oxide. Yabe discloses a metal oxide layer forming method for use in an apparatus, wherein the metal oxide includes aluminum oxide. Both disclose metal oxide layers and transistors and are therefore analogous art. It would be obvious to a POSITA before the effective filing date to select the metal oxide layer of Ishihara to comprise aluminum oxide, as disclosed by Yabe, arriving at the invention as claimed, for the benefit of miniaturizing the transistor (Yabe, Col. 1, lines 23-27).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NIMARTA KAUR CHOWDHARY whose telephone number is (571)272-7679. The examiner can normally be reached usually Monday - Thursday, 6:45 AM - 4:45 PM (EST).
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/NIMARTA KAUR CHOWDHARY/Examiner, Art Unit 2898
/Leonard Chang/
Supervisory Patent Examiner, Art Unit 2898
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