Prosecution Insights
Last updated: July 17, 2026
Application No. 18/889,569

CIRCUIT CARRIER AND METHOD

Non-Final OA §102
Filed
Sep 19, 2024
Priority
Sep 21, 2023 — DE 10 2023 209 201.8
Examiner
NORRIS, JEREMY C
Art Unit
Tech Center
Assignee
Vitesco Technologies GmbH
OA Round
1 (Non-Final)
86%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 86% — above average
86%
Career Allowance Rate
857 granted / 991 resolved
+26.5% vs TC avg
Minimal +4% lift
Without
With
+4.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
15 currently pending
Career history
1008
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
58.5%
+18.5% vs TC avg
§102
37.9%
-2.1% vs TC avg
§112
1.8%
-38.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 991 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-5, 8-10, and 12-17 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 2011/0290536 A1 (Kaneko). Kaneko discloses, referring primarily to figure 12, a circuit carrier for at least one electrical component ([0031], [0037]), comprising: a metal substrate layer (21, [0046]), a first electrical insulation layer (12) arranged on the metal substrate layer, a second electrical insulation layer (14) arranged on the first insulation layer, and an electrically conductive layer (15), arranged on the second electrical insulation layer, having at least one conductor track for electrically connecting the at least one electrical component, wherein at least one of the two electrical insulation layers is colored in such a way that the two electrical insulation layers have different colors ([0039], [0067]) [claim 1], wherein at least one of the two electrical insulation layers is colored in such a way that the two electrical insulation layers are recognizable as two distinct insulation layers at least in a cross section, in particular a micro section of the circuit carrier due to their different colors ([0039], [0067]) [claim 2], wherein at least one of the two insulation layers is colored in such a way that the two distinct insulation layers are recognizable with the naked eye ([0039], [0042], [0043], [0067]) [claim 3], wherein the electrical insulation layers (14, 16) are colored using varicolored particles ([0042]-[0043]) [claim 4]., wherein at least one of the two electrical insulation layers is colored in such a way that the color of the colored insulation layer is in a range visible to the human eye ([0039],[0042], [0043], [0067]) [claim 5]. Additionally, Kaneko discloses, a method for producing a circuit carrier for at least one electrical component ([0031], [0037]), comprising the following steps: providing a metal substrate layer (21, [0046]), applying a first electrical insulation layer (12) to the metal substrate layer, applying a second electrical insulation layer (14) to the first electrical insulation layer, and applying an electrically conductive layer (15) to the second electrical insulation layer, wherein the electrically conductive layer comprises at least one conductor track for electrically connecting the at least one electrical component, and wherein at least one of the two electrical insulation layers is colored in such a way that the two electrical insulation layers have different colors ([0039], [0067]) [claim 8], wherein the coloration takes place before the application, during the application, or after the application of the respective electrical insulation layer ([0039], [0042], [0043], [0067]) [claim 9], wherein the coloration takes place in such a way that the two insulation layers are recognizable as two distinct insulation layers at least in a cross section, in particular a micro section, of the circuit carrier due to their different colors ([0039],[0067]) [claims 10, 17]. Moreover, Kaneko discloses, a method for ascertaining a number of insulation layers in a circuit carrier, in particular in a circuit carrier as claimed in claim 1 (as described above), comprising the following steps: preparing a cross section, in particular a micro section, of the circuit carrier, and ascertaining the number of insulation layers in the circuit carrier on the basis of different colors of the insulation layers ([0039], [0042], [0043], [0067]) [claim 12], wherein the preparation of a micro section of the circuit carrier comprises the following steps: exposing a cross-sectional surface (figure 12), in particular a full cross section of the circuit carrier, and preparing the cross-sectional surface to ascertain the number of insulation layers [claim 13], wherein to ascertain the number of insulation layers in the circuit carrier, the circuit carrier or at least one insulation layer of the circuit carrier is colored ([0039], [0042], [0043], [0067]) [claims 14, 16], wherein the coloration takes place before or after the preparation of the cross section or micro section ([0039], [0042], [0043], [0067]) [claim 15]. Allowable Subject Matter Claims 6, 7, and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Claims 6 and 7 state the limitation “a further, in particular fourth electrical insulation layer, which is arranged on the third insulation layer, and a further, in particular second electrically conductive layer, which is arranged on the fourth electrical insulation layer and comprises at least one further electrical conductor track for electrically connecting the at least one electrical component.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Claim 11 states the limitation “applying a further, in particular second electrically conductive layer having a conductor track for electrically connecting the at least one electrical component to the fourth electrical insulation layer, and coloring the third and/or fourth insulation layer in such a way that the two electrical insulation layers have different colors.” This limitation, in conjunction with the other claimed features, was neither found to be disclosed in, nor suggested by the prior art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JEREMY C NORRIS whose telephone number is (571)272-1932. The examiner can normally be reached 7:15-15:15 M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571)272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JEREMY C. NORRIS Examiner Art Unit 2847 /JEREMY C NORRIS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Sep 19, 2024
Application Filed
Sep 19, 2024
Response after Non-Final Action
Jun 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
86%
Grant Probability
91%
With Interview (+4.5%)
2y 4m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 991 resolved cases by this examiner. Grant probability derived from career allowance rate.

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