Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgement is made to claim of priority to Korean Patent Application No. 10-2024-0067522 filed on May 24, 2024. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on September 19, 2024 is being considered by the examiner.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 14-15 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. With respect to claims 14-15, the Examiner does not understand the written description describing an embodiment that includes all limitations of claim 14 and 15. The limitation “a second interfacial film interposed between the plurality of gate electrodes and the channel film and extending in the first direction;” appears to reference element 152 which appears in the embodiments of Fig. 5 and 6 described in recited in independent claim 11 upon which claims 14-15 depends but does not appear in Fig. 7. The limitations “wherein the second data storage film includes a tunneling insulating film, a charge storage film, and a blocking insulating film, sequentially stacked on the channel film” of claim 14 and “further comprising a gate dielectric film interposed between the blocking insulating film and the plurality of gate electrodes” of claim 15 only appear in the embodiment of Fig. 7, not Fig. 5 or 6.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the the limitations “wherein the second data storage film includes a tunneling insulating film, a charge storage film, and a blocking insulating film, sequentially stacked on the channel film” of claim 14 and “further comprising a gate dielectric film interposed between the blocking insulating film and the plurality of gate electrodes” of claim 15 must be shown in the same embodiment as the limitation “ a second interfacial film interposed between the plurality of gate electrodes and the channel film and extending in the first direction” of claim 11 upon which claims 14-15 depend or the features canceled from the claims. No new matter should be entered.
The drawings are objected to because the labeling of Fig. 15 does not match the description of Fig. 15 in para [00138]. The written description reads “the channel hole CHh may be filled with the third interfacial film 153, the charge storage film 132.2, the second data storage film 132, the second interfacial film 152, the channel film 130, the first interfacial film 151 and the conductive pillar P in this order” (emphasis added). Fig. 15 shows element 131.1 (tunnel insulating film) between 132.2 and 152, not second data storage film 132.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 3-4, and 7-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Son (US 2021/0066344 A1).
With respect to claim 1, Son teaches in Fig. 18:
A semiconductor memory device comprising: a substrate (first substrate 100);
a stack structure disposed on the substrate, wherein the stack structure includes a plurality of gate electrodes (gate electrodes 412, 414, and 416) stacked on each other and spaced apart from each other (spaced apart by insulation pattern 165);
and a channel structure (pillar 700) disposed in the stack structure and penetrating the plurality of gate electrodes (412, 414, and 416),
wherein the channel structure includes:
a conductive pillar (gate electrode 300) extending in a first direction (1st direction) that is substantially perpendicular to an upper surface of the substrate (100);
a channel film (channel 240) disposed between the plurality of gate electrodes and the conductive pillar and extending in the first direction;
a first interfacial film (tunnel insulation layer 250, which may include silicon oxide [0029]) interposed between the conductive pillar (300) and the channel film (240) and extending in the first direction;
a first data storage film (charge storage layer 260) interposed between the conductive pillar and the first interfacial film and extending in the first direction;
and a second data storage film (charge storage structure 230) interposed between each of the gate electrodes and the channel film and extending in the first direction.
With respect to claim 3, Son further teaches:
wherein the first interfacial film (250) includes a silicon oxide film (250 may include an oxide, e.g., silicon oxide.).
With respect to claim 4, Son further teaches:
wherein the channel film (240) includes a semiconductor material (silicon, [0023]), wherein the first interfacial film includes an oxide of the semiconductor material.
With respect to claim 7, Son further teaches:
wherein the second data storage film includes a tunneling insulating film (tunnel insulation film 220), a charge storage film (charge storage layer 210), and a blocking insulating film (blocking layer 200), sequentially stacked on the channel film (200, 210, and 220).
With respect to claim 8, Son further teaches:
wherein each of the tunneling insulating film and the blocking insulating film includes a silicon oxide film, wherein the charge storage film includes a silicon nitride film ([0029], “Each of the first and second tunnel insulation layers 220 and 250 may include an oxide, e.g., silicon oxide. Each of the first and second charge storage layers 210 and 260 may include a nitride, e.g., silicon nitride. Each of the first and second blocking layers 200 and 270 may include an oxide, e.g., silicon oxide.”).
With respect to claim 9, Son further teaches:
further comprising a gate dielectric film (third blocking layer 400) interposed between the blocking insulating film (200) and the plurality of gate electrodes (412, 414, and 416).
With respect to claim 10, Son further teaches:
wherein the channel structure further includes: a channel pad (conductive pad 320) in contact with one end of the channel film (240); and a capping insulating film (insulating interlayer 310) interposed between the conductive pillar and the channel pad (portion of 310 between 320 and 300).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 5, are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Choi (“An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications” Electronics, February 2024).
With respect to claim 2, Son teaches all limitations of claim 1 upon which claim 2 depends. Son fails to teach:
wherein the first data storage film includes at least one of a ferroelectric film or an electrolyte film.
Choi teaches that it is known to replace the charge trap flash memory layers with a ferroelectric material and that the materials are easy to incorporate into the architecture of charge trap flash memories. (Introduction “Consequently, the NAND flash memory structure utilizing ferroelectric memory retains the fundamental advantage of seamlessly preserving the existing NAND flash memory structure and operational methodology.”) It would be obvious to substitute the data storage film of Son with the ferroelectric film taught by Choi to meet the limitation:
wherein the first data storage film includes at least one of a ferroelectric film or an electrolyte film.
Son discloses the claimed invention except for the storage material being a ferroelectric. Choi teaches that it is known to replace the ONO structure of CTF flash memory with ferroelectric materials as described in para. 4 of the introduction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son as taught by Choi in order to reduce power consumption and increase operating speed in a way that is compatible with existing architecture (para. 4 of introduction of Choi). See MPEP 2144.
With respect to claim 5, Son teaches all limitations of claim 1 upon which claim 5 depends. Son fails to teach:
wherein the second data storage film includes a ferroelectric film.
Choi teaches that it is known to replace the charge trap flash memory layers with a ferroelectric material and that the materials are easy to incorporate into the architecture of charge trap flash memories. (Introduction “Consequently, the NAND flash memory structure utilizing ferroelectric memory retains the fundamental advantage of seamlessly preserving the existing NAND flash memory structure and operational methodology.”) It would be obvious to substitute the data storage film of Son with the ferroelectric film taught by Choi to meet the limitation:
wherein the second data storage film includes a ferroelectric film.
Son discloses the claimed invention except for the storage material being a ferroelectric. Choi teaches that it is known to replace the ONO structure of CTF flash memory with ferroelectric materials as described in para. 4 of the introduction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son as taught by Choi in order to reduce power consumption and increase operating speed in a way that is compatible with existing architecture (para. 4 of introduction of Choi). See MPEP 2144.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Choi (“An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications” Electronics, February 2024) as applied to claim 5 above and further in view of Guo (US 12317503 B2).
With respect to claim 6, Son/Choi teach all limitations of claim 5 upon which claim 6 depends. Son/Choi fails to teach:
further comprising a charge storage film and a third interfacial film, each of which are disposed between the second data storage film and the plurality of gate electrodes, and sequentially stacked on the second data storage film.
Guo teaches in Fig. 1B:
a channel film (channel layer 125)
a second interfacial film (buffer layer 124) interposed between the plurality of gate electrodes (gate layer 112) and the channel film (125) and extending in the first direction;
wherein the second data storage film includes a ferroelectric film (ferroelectric layer 123), wherein the channel structure further includes a charge storage film (charge capture layer 122) and a third interfacial film (tunneling layer 121), each of which are disposed between the second data storage film (123) and the plurality of gate electrodes (112) and sequentially stacked on the second data storage film (see Fig. 1B).
Son/Choi discloses the claimed invention except for the structure of the pillar between the channel and the gate electrodes including a interfacial film, ferroelectric film, charge storage film, and additional interfacial film, in that order. Guo teaches that it is known to make an interface between the channel and gate electrodes in a vertical memory with the claimed structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son/Choi as taught by Guo to include the claimed layers between the gate electrodes and channel in order to make a memory layer with versatile storage modes that can be used as a FeRAM or a flash memory (col 3, lns 40-45 of Guo). See MPEP 2144.
Claims 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Lee (US 2021/0111190 A1) and Choi (“An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications” Electronics, February 2024).
With respect to claim 11, Son teaches:
a stack structure disposed on the substrate, wherein the stack structure includes a plurality of gate electrodes (gate electrodes 412, 414, and 416) stacked on each other and spaced apart from each other (spaced apart by insulation pattern 165) in a first direction that is substantially perpendicular to the first surface (1st direction);
and a channel structure (pillar 700) disposed in the stack structure and penetrating the plurality of gate electrodes (412, 414, and 416, wherein the channel structure includes:
a conductive pillar (gate electrode 300) extending in the first direction (1st direction);
a channel film (channel 240) disposed between the plurality of gate electrodes and the conductive pillar and extending in the first direction;
a first data storage film (charge storage layer 260) interposed between the conductive pillar and the channel film (240) and extending in the first direction;
a first interfacial film (tunnel insulation layer 250, which may include silicon oxide [0029]) interposed between the channel film (240) and the first data storage film (260) and extending in the first direction;
a second interfacial film (first tunnel insulation layer 220) interposed between the plurality of gate electrodes (412, 414, 416) and the channel film (240) and extending in the first direction;
and a second data storage film (charge storage layer 210) interposed between each of the gate electrodes (412, 414, 416) and the second interfacial film (220) and extending in the first direction.
Son fails to teach:
a peripheral circuit structure including a peripheral circuit substrate and a peripheral circuit element disposed on the peripheral circuit substrate;
a source layer including a first surface, which faces the peripheral circuit structure, and a second surface that is opposite to the first surface;
wherein the first data storage film includes at least one of a ferroelectric film or an electrolyte film.
Lee teaches in Fig. 2A:
a peripheral circuit structure (peripheral circuit PC) including a peripheral circuit substrate and a peripheral circuit element ([0042] “The peripheral circuit structure PC may include NMOS transistors, PMOS transistors, a resistor, and a capacitor electrically connected to a memory cell array”) disposed on the peripheral circuit substrate;
a source layer (source film) including a first surface (bottom), which faces the peripheral circuit structure (PC), and a second surface (top) that is opposite to the first surface;
Son discloses the claimed invention except for the peripheral circuit structure and source layer. Lee teaches that it is known to include a peripheral circuit structure and source layer in a memory device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son to include a peripheral circuit structure and source layer as taught by Lee in order to read and write the memory cells. See MPEP 2144.
Choi teaches that it is known to replace the charge trap flash memory layers with a ferroelectric material and that the materials are easy to incorporate into the architecture of charge trap flash memories. (Introduction “Consequently, the NAND flash memory structure utilizing ferroelectric memory retains the fundamental advantage of seamlessly preserving the existing NAND flash memory structure and operational methodology.”) It would be obvious to substitute the data storage film of Son/Lee with the ferroelectric film taught by Choi to meet the limitation:
wherein the first data storage film includes at least one of a ferroelectric film or an electrolyte film.
Son/Lee discloses the claimed invention except for the storage material being a ferroelectric. Choi teaches that it is known to replace the ONO structure of CTF flash memory with ferroelectric materials as described in para. 4 of the introduction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son/Lee as taught by Choi in order to reduce power consumption and increase operating speed in a way that is compatible with existing architecture (para. 4 of introduction of Choi). See MPEP 2144.
With respect to claim 12,
It would be further obvious to substitute the data storage film of Son/Lee with the ferroelectric film taught by Choi to meet the limitation:
wherein the second data storage film includes a ferroelectric film.
It would have been obvious to one having ordinary skill in the effective filing date of the claimed invention to combine Son in view of Lee and Choi as explained above.
With respect to claim 14, Son further teaches:
wherein the second data storage film includes a tunneling insulating film (tunnel insulation layer 220), a charge storage film (charge storage layer 210), and a blocking insulating film (200), sequentially stacked on the channel film (240).
With respect to claim 15, Son further teaches:
further comprising a gate dielectric film (third blocking layer 400) interposed between the blocking insulating film (200) and the plurality of gate electrodes (412, 414, and 416).
With respect to claim 16, Son further teaches:
wherein the channel structure further includes: a channel pad (conductive pad 320) in contact with one end of the channel film (240); and a capping insulating film (insulating interlayer 310) interposed between the conductive pillar and the channel pad (portion of 310 between 320 and 300).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Lee (US 2021/0111190 A1) and Choi (“An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications” Electronics, February 2024) as applied to claim 12 above and further in view of Guo (US 12317503 B2).
With respect to claim 13, Son/Lee/Choi teaches all limitations of claim 12 upon which claim 13 depends. Son/Lee/Choi fails to teach:
further comprising a charge storage film and a third interfacial film,
each of which are disposed between the second data storage film and the plurality of gate electrodes, and sequentially stacked on the second data storage film.
Guo teaches:
a channel film (channel layer 125)
a second interfacial film (buffer layer 124) interposed between the plurality of gate electrodes (gate layer 112) and the channel film (125) and extending in the first direction;
further comprising a charge storage film (charge capture layer 122) and a third interfacial film (tunneling layer 121), each of which are disposed between the second data storage film (ferroelectric film 123) and the plurality of gate electrodes (112) and sequentially stacked on the second data storage film (see Fig. 1B).
Son/Lee/Choi discloses the claimed invention except for the structure of the pillar between the channel and the gate electrodes including a interfacial film, ferroelectric film, charge storage film, and additional interfacial film, in that order. Guo teaches that it is known to make an interface between the channel and gate electrodes in a vertical memory with the claimed structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son/Lee/Choi as taught by Guo to include the claimed layers between the gate electrodes and channel in order to make a memory layer with versatile storage modes that can be used as a FeRAM or a flash memory (col 3, lns 40-45 of Guo). See MPEP 2144.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Lee (US 2021/0111190 A1).
With respect to claim 17, Son teaches:
An electronic system comprising:
a main substrate (substrate 100);
a stack structure disposed on the substrate, wherein the stack structure includes a plurality of gate electrodes (gate electrodes 412, 414, and 416) stacked on each other and spaced apart from each other (spaced apart by insulation pattern 165) in a first direction (1st direction);
and a channel structure (pillar 700) disposed in the stack structure and penetrating the plurality of gate electrodes (412, 414, and 416),
wherein the channel structure includes:
a conductive pillar (gate electrode 300) extending in a first direction (1st direction);
a channel film (channel 240) disposed between the plurality of gate electrodes and the conductive pillar and extending in the first direction;
a first interfacial film (tunnel insulation layer 250, which may include silicon oxide [0029]) interposed between the conductive pillar (300) and the channel film (240) and extending in the first direction;
a second interfacial film (insultation film 220) interposed between the plurality of gate electrodes (412, 414, 416) and the channel film (240) and extending in the first direction;
a first data storage film (charge storage layer 260) interposed between the conductive pillar (300) and the first interfacial film (250) and extending in the first direction;
and a second data storage film (charge storage structure 220) interposed between the plurality of gate electrodes (412, 414, 416) and the second interfacial film (210) and extending in the first direction.
Son fails to teach:
a semiconductor memory device including a peripheral circuit structure and a cell structure sequentially stacked on the main substrate;
and a controller disposed on the main substrate and electrically connected to the semiconductor memory device,
Lee teaches in Fig. 2A:
a semiconductor memory device including a peripheral circuit structure (peripheral circuit structure PC) and a cell structure (stack CE) sequentially stacked on the main substrate (substrate SUB);
and a controller (memory controller 1110) disposed on the main substrate and electrically connected to the semiconductor memory device,
Son discloses the claimed invention except for the peripheral circuit structure and controller. Lee teaches that it is known to include a peripheral circuit structure and controller in a memory device. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son to include a peripheral circuit structure and controller as taught by Lee in order to read and write the memory cells. See MPEP 2144.
With respect to claim 18, Son/Lee further teaches in Fig. 27-28 of Son:
wherein the controller is configured to apply different voltages to the plurality of gate electrodes (word lines, see Fig. 28) and the conductive pillar (back gate, which for example has voltage Vpgm applied to it in para. [0121]), respectively.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Lee (US 2021/0111190 A1) as applied to claim 17 above and further in view of Choi (“An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications” Electronics, February 2024).
With respect to claim 19, Son/Lee teaches all limitations of claim 17 upon which claim 19 depends. Son/Lee fails to teach:
wherein each of the first data storage film and the second data storage film includes a ferroelectric film.
Choi teaches that it is known to replace the charge trap flash memory layers with a ferroelectric material and that the materials are easy to incorporate into the architecture of charge trap flash memories. (Introduction “Consequently, the NAND flash memory structure utilizing ferroelectric memory retains the fundamental advantage of seamlessly preserving the existing NAND flash memory structure and operational methodology.”) It would be obvious to substitute the data storage film of Son/Lee with the ferroelectric film taught by Choi to meet the limitation:
wherein each of the first data storage film and the second data storage film includes a ferroelectric film.
Son/Lee discloses the claimed invention except for the storage material being a ferroelectric. Choi teaches that it is known to replace the ONO structure of CTF flash memory with ferroelectric materials as described in para. 4 of the introduction. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son/Lee as taught by Choi in order to reduce power consumption and increase operating speed in a way that is compatible with existing architecture (para. 4 of introduction of Choi). See MPEP 2144.
Claims 20 is rejected under 35 U.S.C. 103 as being unpatentable over Son (US 2021/0066344 A1) in view of Lee (US 2021/0111190 A1) as applied to claim 17 above and further in view of Guo (US 12317503 B2).
With respect to claim 20, Son/Lee teaches all limitations of claim 17 upon which claim 20 depends. Son/Lee fails to teach:
wherein the second data storage film includes a ferroelectric film, wherein the channel structure further includes a charge storage film and a third interfacial film, each of which are disposed between the second data storage film and the plurality of gate electrodes and sequentially stacked on the second data storage film.
Guo teaches:
a channel film including a ferroelectric film(channel layer 125)
a second interfacial film (buffer layer 124) interposed between the plurality of gate electrodes (gate layer 112) and the channel film (125) and extending in the first direction;
wherein the second data storage film includes a ferroelectric film (ferroelectric layer 123), wherein the channel structure further includes a charge storage film (charge capture layer 122) and a third interfacial film (tunneling layer 121), each of which are disposed between the second data storage film (123) and the plurality of gate electrodes (112) and sequentially stacked on the second data storage film (see Fig. 1B).
Son/Lee discloses the claimed invention except for the structure of the pillar between the channel and the gate electrodes including a interfacial film, ferroelectric film, charge storage film, and additional interfacial film, in that order. Guo teaches that it is known to make an interface between the channel and gate electrodes in a vertical memory with the claimed structure. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Son/Lee as taught by Guo to include the claimed layers between the gate electrodes and channel in order to make a memory layer with versatile storage modes that can be used as a FeRAM or a flash memory (col 3, lns 40-45 of Guo). See MPEP 2144.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AARON MICHAEL WEGNER whose telephone number is (571)270-7647. The examiner can normally be reached Mon-Fri 8:30 AM - 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at (469) 295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
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