Prosecution Insights
Last updated: October 04, 2026
Application No. 18/889,802

ELECTRONIC DEVICE

Non-Final OA §102
Filed
Sep 19, 2024
Priority
Dec 27, 2017 — continuation of 10/193,042 +3 more
Examiner
TRAN, TIEN
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Innolux Corporation
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
1y 1m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
24 granted / 26 resolved
+24.3% vs TC avg
Moderate +10% lift
Without
With
+10.5%
Interview Lift
resolved cases with interview
Typical timeline
3y 2m
Avg Prosecution
31 currently pending
Career history
48
Total Applications
across all art units

Statute-Specific Performance

§101
2.2%
-37.8% vs TC avg
§103
66.5%
+26.5% vs TC avg
§102
19.6%
-20.4% vs TC avg
§112
8.4%
-31.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 26 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . DETAILED ACTION Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-9 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable over US20140367633A1; Bibl et al.; (hereinafter “Bibl”). Regarding Claim 1, Bibl teaches an electronic device ([0053]), comprising: a substrate (#201, Figure 13A of Bibl annotated); a driving circuit (#210, see also Figure 1C, [0060]) disposed on the substrate (#102); a diode (#400) disposed on the substrate (#102) and electrically connected to the driving circuit (#210, see also Figure 1D); an optical layer (#310) disposed on the diode (#400) and comprising a first curved surface (#S1), a light shielding element (#202) disposed on the substrate (#102) and adjacent to the optical layer (#202); and an inorganic layer (#324, [0102]) disposed on the substrate (#102), PNG media_image1.png 735 1158 media_image1.png Greyscale wherein the inorganic layer (#324) overlaps the optical layer (#310) and the light shielding element (#202), and the inorganic layer (#324) comprises a second curved surface (#S2) overlapping the first curved surface (#S1). Regarding Claim 2, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches a surface of the light shielding element has a first width, a horizontal cross-section of a portion of the light shielding element has a second width, the second width is greater than the first width in a cross-sectional view, and the surface is closer to the substrate than the horizontal cross-section of the portion. Regarding Claim 3, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches the optical layer comprises quantum dot materials ([0102], layer #310 comprises quantum dots). Regarding Claim 4, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches the driving circuit comprises a first thin-film transistor and a second thin-film transistor (Figure 1C-D, [0060], underlying TFT substrate #102 comprises circuitries #T1-T2). Regarding Claim 5, Bibl teaches the electronic device as described in claim 4, wherein Bibl further teaches the diode (#400,) overlaps a channel region of the first thin-film transistor (Figure 1C-D, micro LED #400 vertically overlaps active region of TFT circuit #T2). Regarding Claim 6, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches the optical layer (#310, Figure 13A) overlaps the diode (#400). Regarding Claim 7, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches an organic layer (#126, Figure 13A, [0062]), wherein a portion of the organic layer (#126) is disposed between the driving circuit (#210) and the light shielding element (#202). Regarding Claim 8, Bibl teaches the electronic device as described in claim 7, wherein Bibl further teaches an another portion of the organic layer (#126, Figure 13A) is disposed between the driving circuit (#210) and the optical layer (#310). Regarding Claim 9, Bibl teaches the electronic device as described in claim 1, wherein Bibl further teaches the light shielding element comprises a black matrix material ([0109], black matrix layer #202). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. US20140159043A1 – Figures 6B-7B US9472734A1 – Figures 5-6 Any inquiry concerning this communication or earlier communications from the examiner should be directed to TIEN TRAN whose telephone number is (571)272-6967. The examiner can normally be reached Monday-Thursday 9:00 am - 6:00 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, CHRISTINE S KIM can be reached on (571)272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /TIEN TRAN/Examiner, Art Unit 2812 /CHRISTINE S. KIM/Supervisory Patent Examiner, Art Unit 2812
Read full office action

Prosecution Timeline

Sep 19, 2024
Application Filed
Sep 21, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Patent 12690214
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
99%
With Interview (+10.5%)
3y 2m (~1y 1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 26 resolved cases by this examiner. Grant probability derived from career allowance rate.

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