DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 09/19/2024 is being considered by the examiner.
Priority
Acknowledgement is made to claim of priority to Korean Patent Application No. 10-2024-0016494.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee-485 (US 2023/0009485 A1).
With respect to claim 1, Lee-485 teaches:
A semiconductor device comprising:
a substrate (substrate 20) comprising an N-type region (59-1) and a P-type region (59-2) ([0043] “ device regions 59-1 and 59-2 may be an n-type transistor region and a p-type transistor region, respectively,”);
a first active pattern on the N-type region (left stack of 22b in transistor 92-1);
a first gate structure on the N-type region (See Fig. 24a, gate dielectrics 62, protection layer 64, stacked conductive layers 76, filling metal 78 associated with first active pattern),
the first gate structure crossing the first active pattern and comprising fluorine (F) (Fig. 25 shows the distribution of fluorine after fluorine-containing layer 66 is deposited and before the anneal, showing that there is fluorine in dielectric 62 of both gate structures);
a second active pattern on the P-type region (left stack of 22b in transistor 92-2);
and a second gate structure on the P-type region (see Fig. 24A, gate dielectrics 62, protection layer 64, stacked conductive layers 76, filling metal 78),
the second gate structure crossing the second active pattern and comprising fluorine (F) (see Fig. 25-27),
wherein the first gate structure comprises a first gate dielectric film (gate dielectrics 62 in 59-1) on the first active pattern,
and a first gate electrode (conductive layer 76 and filling metal 78 on associated with the first active pattern on 59-1) on the first gate dielectric film,
wherein the second gate structure comprises a second gate dielectric film (gate dielectrics 62 in 59-2) on the second active pattern and a second gate electrode (conductive layers 76 and filling metal 78 on associated with the second active pattern on 59-2) on the second gate dielectric film,
and wherein a fluorine (F) concentration of the second gate dielectric film is smaller than a fluorine (F) concentration of the first gate dielectric film ([0055] “the gate dielectrics 62 in device region 59-1 have an increased fluorine atomic percentage FAP1, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAP2 in the gate dielectrics 62 in device regions 59-2.”).
With respect to claim 2, Lee-485 further teaches:
wherein the first active pattern comprises at least one first bridge pattern spaced apart from the substrate and passing through the first gate structure,
and wherein the second active pattern comprises at least one second bridge pattern spaced apart from the substrate and passing through the second gate structure (See Fig. 19B, active patterns 22B pass through gate and are separated from the substrate in a gate all around configuration).
With respect to claim 3, Lee-485 further teaches:
wherein the first gate dielectric film (62 in 59-1) comprises a first high dielectric film (high-k dielectric 62B) having a dielectric constant greater than a dielectric constant of silicon oxide,
wherein the second gate dielectric film (62 in 59-2) comprises a second high dielectric film (62B) having a dielectric constant greater than the dielectric constant of silicon oxide,
and wherein a fluorine (F) concentration of the second high dielectric film is smaller than a fluorine (F) concentration of the first high dielectric film ([0055] “the gate dielectrics 62 in device region 59-1 have an increased fluorine atomic percentage FAP1, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAP2 in the gate dielectrics 62 in device regions 59-2”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4 and 11-15 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-485 (US 2023/0009485 A1) in view of Lee-686 (US 2022/0238686 A1).
With respect to claim 4, Lee-485 teaches all limitations of claim 1 upon which claim 4 depends. Lee-485 further teaches:
wherein the first gate electrode comprises a first work function control film (stacked conductive layer 76 on 92-1) on the first gate dielectric film (62 of 92-1),
and a first filling film (filling metal 78 on 92-1) on the first work function control film (76),
wherein the second gate electrode comprises a second work function control film (76 on 92-2) on the second gate dielectric film (62 on 92-2),
and a second filling film (78 on 92-2) on the second work function control film (76 on 92-2),
Lee-485 fails to teach:
and wherein the first filling film and the second filling film do not contain fluorine (F).
Lee-686 further teaches:
and wherein the first filling film and the second filling film do not contain fluorine (F). (Lee-686 teaches in [0084] that the outer layers may be free of fluorine because they are formed after the fluorination process)
Lee-485 discloses the claimed invention except for the filling layers being fluorine-free. Lee-686 teaches that it is known to make a gate structure such that the gate layers deposited after the fluorine treatment do not contain fluorine. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-485 as taught by Lee-686 to make filling layers that do not contain fluorine for the purpose of tuning the work function metal by adjusting the fluorine content of each layer of the gate stack. See MPEP 2144.
With respect to claim 11, Lee-485 teaches in Fig. 16-27:
A semiconductor device comprising:
a substrate (see for example Fig. 16, substrate 20) comprising a first region (device region 59-2) and a second region (device region 59-1);
a first transistor (GAA transistor 92-2) on the first region (59-2), the first transistor having a first threshold voltage ([0015] “a fluorine treatment is applied to one or more gate dielectric layers of a gate structure, and a dipole dopant species is diffused into the gate dielectric layers, thereby tuning the work functions (and thus threshold voltages) of the subsequently formed transistors”);
and a second transistor (GAA transistor 92-1) on the second region (59-1),
wherein the first transistor comprises a first active pattern (22b) and a first gate (See Fig. 24a, gate dielectrics 62, protection layer 64, stacked conductive layers 76, filling metal 78) structure crossing the first active pattern,
the first gate structure comprising fluorine (F) (Fig. 25 shows the distribution of fluorine after fluorine-containing layer 66 is deposited and before the anneal, showing that there is fluorine in dielectric 62 of both gate structures)
wherein the second transistor comprises a second active pattern (second layer 22b) and a second gate structure crossing the second active pattern (see Fig. 24A, gate dielectrics 62, protection layer 64, stacked conductive layers 76, filling metal 78),
the second gate structure comprising fluorine (F) (see Fig. 25-27),
and wherein a fluorine (F) concentration of the first gate structure is different from a fluorine (F) concentration of the second gate structure ([0055] “the gate dielectrics 62 in device region 59-1 have an increased fluorine atomic percentage FAP1, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAP2 in the gate dielectrics 62 in device regions 59-2.”)
Although Lee-485 teaches that threshold voltage is tuned by introducing fluorine, Lee does not teach which
the second transistor having a second threshold voltage lower than the first threshold voltage,
Lee-686 teaches that fluorine treatment reduces the threshold voltage of a transistor:
[0014] “An aluminum treatment is performed on the WFM layer before the fluorine treatment to increase the effectiveness of the fluorine treatment. As a result, a flatband voltage (V.sub.FB) of the resulting transistor can be increased towards a band edge of the metal of the WFM layer, a threshold voltage of the resulting transistor can be decreased, and device performance may be improved.”
It would be obvious to tune the threshold voltages of the first and second transistor such that the second threshold voltage is lower than the first threshold voltage as claimed since Lee-485 teaches that the second transistor has higher fluorine concentration and Lee-686 teaches that higher fluorine concentration leads to lower threshold voltage. It would be obvious to make such a modification for the purpose of fabricating transistors with different voltage needs on the same substrate.
With respect to claim 12, Lee-485 further teaches:
wherein the first active pattern comprises at least one first bridge pattern spaced apart from the substrate and passing through the first gate structure,
and wherein the second active pattern comprises at least one second bridge pattern spaced apart from the substrate and passing through the second gate structure (See Fig. 19B, active patterns 22B pass through gate and are separated from the substrate in a gate all around configuration).
With respect to claim 13, Lee-485 further teaches:
wherein the first gate structure comprises a first work function control film (stacked conductive layer 76 on 92-2) on the first active pattern (22B of 92-2),
and a first filling film (filling metal 78) on the first work function control film (76),
wherein the second gate structure comprises a second work function control film (76 on 92-1) on the second active pattern (22B),
and a second filling film (78 on 92-1) on the second work function control film (76 on 92-1),
Lee-686 further teaches:
and wherein the first filling film and the second filling film do not contain fluorine (F). (Lee-686 teaches in [0084] that the outer layers may be free of fluorine because they are formed after the fluorination process)
Lee-485 discloses the claimed invention except for the filling layers being fluorine-free. Lee-686 teaches that it is known to make a gate structure such that the gate layers deposited after the fluorine treatment do not contain fluorine. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify Lee-485 as taught by Lee-686 to make filling layers that do not contain fluorine for the purpose of tuning the work function metal by adjusting the fluorine content of each layer of the gate stack. See MPEP 2144.
With respect to claim 14, Lee-485 further teaches:
wherein the first region and the second region are P-type regions ([0043] “both of device regions 59-1 and 59-2 are p-type transistor regions.”),
and wherein a fluorine (F) concentration of the second work function control film (76 in 92-1) is greater than a fluorine (F) concentration of the first work function control film (76 of 92-2) ([0055] “the gate dielectrics 62 in device region 59-1 have an increased fluorine atomic percentage FAP1, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAP2 in the gate dielectrics 62 in device regions 59-2.” Fluorine in 76 is due to diffusion from 62, therefore the layer 76 with more fluorine will be in transistor 92-1)
With respect to claim 15, Lee-485 further teaches:
wherein the first region and the second region are N-type regions ([0043] “both of device regions 59-1 and 59-2 are n-type transistor regions”),
and wherein a fluorine (F) concentration of the second work function control film (76 in 92-1) is greater than a fluorine (F) concentration of the first work function control film (76 of 92-2) ([0055] “the gate dielectrics 62 in device region 59-1 have an increased fluorine atomic percentage FAP1, which fluorine atomic percentage is also higher than the fluorine atomic percentage FAP2 in the gate dielectrics 62 in device regions 59-2.” Fluorine in 76 is due to diffusion from 62, therefore the layer 76 with more fluorine will be in transistor 92-1)
Claims 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee-485 (US 2023/0009485 A1) in view of Lee-686 (US 2022/0238686 A1) as applied to claim 4 above and further in view of Song (US 2019/0189767 B2).
With respect to claim 5, Lee-485/Lee-686 teaches all limitations of claim 4 upon which claim 5 depends. Lee-485/Lee-686 fails to teach:
wherein a thickness of the second work function control film is greater than a thickness of the first work function control film.
Song teaches that it is known to adjust the work function of the gate electrode by changing the thickness of the work function control film ([0043] “where the first work function metal layers (140, 240, 340, 440) of the gate structures GS1 to GS4 have different thicknesses (W1, W2, W3, W4).”)
It would be obvious to choose thicknesses of the work function control films to meet the limitation:
wherein a thickness of the second work function control film is greater than a thickness of the first work function control film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the thicknesses of work function control films to meet the above limitation with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). The ordinary artisan would be motivated to modify the thicknesses of the work function control films because Song teaches that the thicknesses are a results effective variable that can be used to tune the effective work function of gate electrodes.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Lee-485 (US 2023/0009485 A1) in view of Lee-686 (US 2022/0238686 A1) as applied to claim 4 above and further in view of Cheng (US 2016/0225871 A1).
With respect to claim 6, Lee-485/Lee-686 teaches all limitations of claim 5 upon which claim 6 depends. Lee-485/Lee-686 fails to teach:
wherein the first work function control film comprises a first work function insulating film on the first gate dielectric film,
and a first work function conductive film on the first work function insulating film,
wherein the second work function control film comprises a second work function insulating film on the second gate dielectric film,
and a second work function conductive film on the second work function insulating film,
and wherein a fluorine (F) concentration of the second work function insulating film is smaller than a fluorine (F) concentration of the first work function insulating film.
Cheng teaches in Fig. 2:
wherein the first work function control film (work function metallic layer 223 and first high k capping layer 221C) comprises a first work function insulating film (221C) on the first gate dielectric film (high K dielectric layer 221B);
and a first work function conductive film (223) on the first work function insulating film (221C),
wherein the second work function control film (work function metallic layer 233 and second high-k capping layer 231C) comprises a second work function insulating film (231C) on the second gate dielectric film (high k dielectric layer 231B),
and a second work function conductive film (223) on the second work function insulating film (231C),
Cheng teaches that the fluorine concentration of the work function insulating film is results effective for tuning the effective work function of a gate electrode ([0011] “In certain embodiments, when the metal-oxide semiconductor structure 100 is used as a p-type MOS (PMOS) transistor device and the fluorine concentration is within a range from about 1 at % to about 10 at %, a threshold voltage of the PMOS transistor device may be reduced in a range from about 25 mV to 100 mV. In alternative embodiments, when the metal-oxide semiconductor structure 100 is used as a n-type MOS (NMOS) transistor device and the fluorine concentration is within a range from about 1 at % to about 10 at %, a threshold voltage of the NMOS transistor device may be increased in a range from about 25 mV to 100 mV. In some embodiments, the fluorine concentration may be within a range from about 1 at % to about 4 at %.).
Lee-485/Lee-686 discloses the claimed invention except for the work function insulating layer between the high-k dielectric and work function conductive layer. Cheng teaches that it is known to include a fluorinated work function insulating layer between the high-k dielectric layer and work function conductive layer as shown in Fig. 2. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to include a work function insulating layer between the high k dielectric layer and work function conductive layer, as taught by Cheng in order to tune the effective work function of the gate electrode. See MPEP 2144.
It would be further obvious to choose fluorine concentration of the work function insulating films to meet the limitation:
and wherein a fluorine (F) concentration of the second work function insulating film is smaller than a fluorine (F) concentration of the first work function insulating film.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to adjust the fluorine of work function insulating films to meet the above limitation with routine experiment and optimization. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). The ordinary artisan would be motivated to modify the thicknesses of the work function control films because Cheng teaches that the fluorine concentrations are a results effective variable that can be used to tune the effective work function of gate electrodes.
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Lee-485 (US 2023/0009485 A1).
With respect to claim 8, Lee-485 teaches all limitations of claim 1 upon which claim 8 depends. Lee-485 does not teach:
a third active pattern on the P-type region (right stack of 22b in transistor 92-2);;
and a third gate structure on the P-type region (See Fig. 24a, gate dielectrics 62, protection layer 64, stacked conductive layers 76, filling metal 78 associated with third active pattern),
the third gate structure crossing the third active pattern and comprising fluorine (F) (see Fig. 25-27),
wherein the third gate structure comprises a third gate dielectric film on the third active pattern (gate dielectrics 62 in 59-1),
and a third gate electrode (78) on the third gate dielectric film,
Lee-485 does not teach:
and wherein a fluorine (F) concentration of the third gate electrode is different from the fluorine (F) concentration of the second gate electrode.
However, Lee-485 teaches that fluorine concentration is results effective in tuning the effective work function of the gate electrodes. It would be obvious to modify Lee-485 such that the third gate electrode has a different fluorine concentration than the second electrode for the purpose of making transistors with different threshold voltages on the substrate.
With respect to claim 9, Lee-485 as modified in above teaches:
a first transistor comprising the second active pattern and the second gate structure, the first transistor having a first threshold voltage (22B serves as channels in a transistor);
and a second transistor comprising the third active pattern and the third gate structure, the second transistor having a second threshold voltage lower than the first threshold voltage (22B serves as channels in a transistor);
wherein the fluorine (F) concentration of the third gate electrode is greater than the fluorine (F) concentration of the second gate electrode.
Lee-485 does not teach:
and wherein a fluorine (F) concentration of the third gate electrode is greater than the fluorine (F) concentration of the second gate electrode.
However, Lee-485 teaches that fluorine concentration is results effective in tuning the effective work function of the gate electrodes. It would be obvious to modify Lee-485 such that the third gate electrode has a greater fluorine concentration than the second electrode for the purpose of making transistors with different threshold voltages on the substrate.
With respect to claim 10 Lee-485 as modified above teaches:
wherein the second gate electrode (stacked conductive layers 76, filling metal 78 associated with second active region) comprises a first work function control film (76) on the second gate dielectric film (62),
and a first filling film (78) on the first work function control film (76),
wherein the third gate electrode (stacked conductive layers 76, filling metal 78 associated with third active region) comprises a second work function control film (76) on the third gate dielectric film (62), and a second filling film (78)on the second work function control film,
Lee-485 does not teach:
wherein a fluorine (F) concentration of the second work function control film is greater than a fluorine (F) concentration of the first work function control film,
and wherein the first filling film and the second filling film do not contain fluorine (F).
However, Lee-485 teaches that fluorine concentration is results effective in tuning the effective work function of the gate electrodes. It would be obvious to modify Lee-485 such that the second work function control film has a greater fluorine concentration than the first work function control film for the purpose of making transistors with different threshold voltages on the substrate.
Allowable Subject Matter
Claims 7 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-20 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: Regarding claim 7, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “wherein each of the fluorine (F) concentration of the second gate dielectric film and a fluorine (F) concentration of the second work function conductive film are greater than the fluorine (F) concentration of the second work function insulating film“ of claim 7 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Claim 16 includes similar limitations as those found allowable in claim 7 and is indicated as including allowable subject matter for similar reasons.
Regarding claim 17, prior art of record does not fairly disclose or make obvious the claimed device as a whole. Specifically, the closest prior art (which has been made of record) fail to disclose (by themselves or in combination) the limitations of “and wherein a fluorine (F) concentration of the high dielectric film and a fluorine (F) concentration of the work function conductive film are greater than a fluorine (F) concentration of the work function insulating film” of claim 17 in combination with the additionally claimed features, as are claimed by the Applicant. Thus, the Applicant’s claims are determined to be novel and non-obvious.
Claims 18-20 are allowable at least for the same reason as independent claim 17 upon which they depend.
Upon completing a prior art search and considering the combination of limitations as presented as a whole for the claims, the features highlighted above are considered an improvement over the prior art and have not been found to be anticipated or rendered obvious by a combination of prior art.
Conclusion
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/A.M.W./Examiner, Art Unit 2897
/JACOB Y CHOI/Supervisory Patent Examiner, Art Unit 2897
