DETAILED ACTION
Examiner’s Note
The examiner has cited particular passages including column and line numbers, paragraphs as designated numerically and/or figures as designated numerically in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claims, other passages, paragraphs and figures of any and all cited prior art references may apply as well. It is respectfully requested from the applicant, in preparing an eventual response, to fully consider the context of the passages, paragraphs and figures as taught by the prior art and/or cited by the examiner while including in such consideration the cited prior art references in their entirety as potentially teaching all or part of the claimed invention. MPEP 2141.02 VI: “PRIOR ART MUST BE CONSIDERED IN ITS ENTIRETY, INCLUDING DISCLOSURES THAT TEACH AWAY FROM THE CLAIMS." MPEP 2123 (I): “PATENTS ARE RELEVANT AS PRIOR ART FOR ALL THEY CONTAIN.”
Additionally, in an effort to provide a timely Office response to amendments the Applicant may file in response to this Office Action, it is respectfully requested that, on accompanying remarks/arguments papers, every effort be made to provide specific (page No., paragraph No., FIG. No., etc.) Specification/Drawings support for such amendments, particularly claim amendments.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim(s) 1 has been cancelled.
Allowable Subject Matter
Claim(s) 16-17 and 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein performing the access operation further comprises: biasing a gate of a third transistor to a third voltage, wherein the third transistor is coupled with the bit line and a second conductive pillar coupled with a second memory cell; and biasing a gate of a fourth transistor to a fourth voltage, wherein a fourth transistor is coupled with the third transistor and the bit line, and wherein the fourth voltage is less than the second voltage and the third voltage is less than the fourth voltage; while in regard to claim 17, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein performing the access operation further comprises: performing a second access operation for the memory cell, the second access operation comprising: coupling the conductive pillar with the bit line based at least in part on biasing a gate of the first transistor to a third voltage and biasing a gate of the second transistor to the third voltage, wherein the third voltage is less than the first voltage; biasing the bit line to a fourth voltage based at least in part on coupling the conductive pillar with the bit line, wherein the fourth voltage is less than the third voltage; and storing a second value to the memory cell based at least in part on coupling the conductive pillar with the bit line and biasing the bit line to the third voltage; while in regard to claim 19, the pertinent prior art of record does not teach or suggest the whole of the claimed limitations, in complete combination with the base claim and any and all intervening claim limitations: wherein performing the access operation further comprises: biasing, outside of the access operation, a gate of the first transistor to a third voltage; and biasing, outside of the access operation, a gate of the second transistor to a fourth voltage, wherein the fourth voltage is less than the first voltage and the third voltage is less than the fourth voltage.
Claim(s) 18 depends from claim 17, and as such is therefore objected for the same reasons.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 4 is rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, because the specification, while being enabling for, generally, biasing the gate of the first and second transistors, does not reasonably provide enablement for “wherein the third voltage is less than the first voltage and the fourth voltage is less than the third voltage.” The specification does not enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention commensurate in scope with these claims. FIGS. 3A-3B and [0039]-[0041] seem relevant to the claimed subject matter. In brief, it seems disclosed that the first and second transistors may be n-type and “may include different channel types.” There is a universe of two types of transistors n-type and p-type, unless there is also consideration of BJT-type transistors; the latter do not seem to be described in the least in the drawings and specification, therefore, any inclusion thereof in this discussion is limited to naming them. It seems disclosed that these first and second transistors may be biased to enable them or disable them. As an aside, none of this is new in the art, and choosing n-type vs. p-type transistors, or indeed both types does not rise to the level in innovation and does require undue experimentation. Yet, there seems there is no disclosure in the drawings and/or specification that, as claimed, “the fourth voltage is less than the third voltage.”
Claim(s) 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. There does not seem to be antecedent basis for “respective gate lines.” Claim 1, from which claim 5 depends, includes: bit lines, word lines and gate of the second transistor; nevertheless, there is no claim of “respective gate lines,” or to what they may be respective to.
Claim(s) 6 depends from claim 5 and as such is also rejected for the same reasons.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 2-3, 7-15 and 20-21 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 20230154538 to Yang et al. (“Yang”).
As to claim 2, Yang teaches substantially the invention, as claimed, including: An apparatus, comprising: a conductive pillar extending through a plurality of levels of a memory array (As found in at least FIG. 4D: conductive pilar 472 extends through plurality of levels of memory array 202 in at least FIG. 2A, array in FIG. 4A, etc.), wherein, at each level of the plurality of levels, one or more memory cells of the memory array are coupled with the conductive pillar and a respective word line (As found in at least FIG. 4D: cells MCn at each levels coupled to pillar 472 and/or 474 and respective word line WLn); a bit line (As found in at least FIG. 4C: bit line 417); a first transistor coupled with the bit line and the conductive pillar (As found in at least FIGS. 4C and 4F: first transistor having gate SGDT coupled to bit line 414 and pillar 474/472; also see bit line 411 in FIG. 4F); and a second transistor coupled with the bit line and the first transistor (As found in at least FIGS. 4C and 4F: second transistor having gate SGD coupled to bit line 414 and first transistor having gate SGDT; also see bit line 411 in FIG. 4F), the first transistor and the second transistor configured to selectively couple the conductive pillar with the bit line based at least in part on the first transistor and a gate of the second transistor being biased to a first voltage (As found in at least FIG. 4F: in the event SGDT and SGD gates of first and second transistors are biased to turn their respective transistors OFF, coupling of bit line 411 and pillar 472/474 is OFF; in the event SGDT and SGD gates of first and second transistors are biased to turn their respective transistors ON, coupling of bit line 411 and pillar 472/474 is ON; thus, coupling of bit line to pillar is selective), wherein the bit line is biased to a second voltage based at least in part on coupling the conductive pillar with the bit line (As found in at least FIG. 7A and [0119]: SGD and SGDT are applied a VSG voltage, while bit line is applied a second voltage VDDSA).
As to claim 3, Yang teaches wherein to couple the conductive pillar with the bit line, respective gate lines coupled with each of the first transistor and the second transistor are configured to bias a gate of the first transistor and a gate of the second transistor to the first voltage, wherein the first voltage is greater than the second voltage (As found in at least FIG. 7A and [0120]: first voltage is VSG = 6-8 volts, while second voltage is VDDSA = 2.5 volts; VSG > VDDSA).
As to claim(s) 7-8, Yang teaches a second conductive pillar extending through the plurality of levels; a third transistor coupled with the bit line and the second conductive pillar; and a fourth transistor coupled with the bit line and the second conductive pillar; wherein a gate of the third transistor and a gate of the fourth transistor are biased independently from the gate of the first transistor and the gate of the second transistor based at least in part on performing an access operation using the conductive pillar (As found in at least FIGS. 4, 4C, 4D, 4F: plurality of first and second transistors, such as those coupled to gate lines SGDT(s0-s5) and SGD(s0-s5) coupled with bit line 411 and corresponding pillar; also relevant are second set of first and second transistors SGS and SGSB; moreover, gates of first, second, third an fourth transistors are biased independently).
As to claim 9, Yang teaches a conductive line coupled with the conductive pillar and the second conductive pillar, wherein the conductive line is positioned at an end of the conductive pillar and the second conductive pillar opposite the first transistor, the second transistor, the third transistor, and the fourth transistor (As found in at least FIG. 4F: conductive line SL).
As to claim 10, Yang teaches wherein a terminal of the first transistor is coupled with a terminal of the second transistor (As found in at least FIG. 4F: terminal of transistor gated at SGDT is coupled to terminal of transistor gated at SGD).
As to claim 11, Yang teaches wherein the first transistor and the second transistor are arranged in a series configuration between the conductive pillar and the bit line (As found in at least FIGS. 4C, 4D, 4F: transistors gated at SGDT and SGD are in series between pillar 474/472 and bit line 414).
As to claim 12, see rejection to at least claim 2; moreover, the method is inherently taught by the apparatus, and at least in this case, explicitly presented in the claim 2 rejection analysis.
As to claim 13-14, Yang teaches storing a first value to the memory cell based at least in part on coupling the conductive pillar with the bit line and biasing the bit line to the second voltage; wherein biasing the gate of the first transistor and the gate of the second transistor to the first voltage further comprises: biasing a respective gate line coupled with each of the first transistor and the second transistor to the first voltage. (As found in at least FIG. 7A and [0024], [0119]: timing diagram “as part of the programming process;” where the first and second transistors gated at SGD and SGDT are enabled biased at VSG and the bit line is biased to VDDSA).
As to claim 15, Yang teaches wherein a difference between the first voltage and the second voltage satisfies a threshold voltage of the first transistor and the second transistor (As found in at least FIG. 7A and [0120]: first voltage is VSG = 6-8 volts, while second voltage is VDDSA = 2.5 volts; therefore, the difference of about 3.5-5.5 clearly satisfies the first and second transistor threshold voltage).
As to claim 20, see rejection to at least claim(s) 2 and 12; moreover, Yang in at least FIGS. 1-3 teaches one or more controllers associated with a memory device (Controller 120 controlling memory 130).
As to claim 21, see rejection to at least claim(s) 13-14.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claim(s) 2-21 rejected on the ground of nonstatutory double patenting as being unpatentable over claim(s) 1, 17 of U.S. Patent No. 11967372; unpatentable over claim(s) 1, 14, 19 of U.S. Patent No. 12119056 . Although the claims at issue are not identical, they are not patentably distinct from each other because the instant claims are obviated by the patented claims. A later patent claim is not patentably distinct from an earlier patent claim if the later claim is obvious over (in a non-statutory double patent rejection) the earlier claim. In re Lonqi, 759 F.2d at 896, 225 USPQ at 651 (affirming a holding of obviousness-type double patenting because the claims at issue were obvious over claims in four prior art patents); In re Bercl, 140 F.3d at 1437, 46 USPQ2d at 1233 (Fed. Cir. 1998) (affirming a holding of obviousness-type double patenting where a patent application claim to a genus is anticipated by a patent claim to a species within that genus). Ely Lilly and Co. v Bar Laboratories, Inc., United States Court of Appeals for the Federal Circuit, on petition for rehearing en banc (decided: May 30, 2001).The instant claims are obviated by the patented claims; the patent and the application claim obvious common subject matter; in brief and saliently: apparatus, and/or method thereof, comprising, in brief and saliently: a conductive pillar extending through a plurality of levels of a memory array; one or more memory cells of the memory array are coupled with the conductive pillar at each level; a bit line; first and second transistors coupled between the bit line and the pillar, where the transistors gates are biased in memory operations.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FERNANDO N HIDALGO whose telephone number is (571)270-3306. The examiner can normally be reached M-F 9:00-7:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 5712721852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
FERNANDO N. HIDALGO
Primary Examiner
Art Unit 2827
/Fernando Hidalgo/Primary Examiner, Art Unit 2827