Prosecution Insights
Last updated: October 22, 2026
Application No. 18/890,180

Substrate Processing Apparatus, Substrate Processing Method, Method of Manufacturing Semiconductor Device and Non-transitory Computer-readable Recording Medium

Non-Final OA §103
Filed
Sep 19, 2024
Priority
Mar 29, 2022 — JP 2022-053818 +1 more
Examiner
RODRIGUEZ, MICHAEL P
Art Unit
1712
Tech Center
1700 — Chemical & Materials Engineering
Assignee
Kokusai Electric Corporation
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
7m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allowance Rate
501 granted / 683 resolved
+8.4% vs TC avg
Strong +29% interview lift
Without
With
+29.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 8m
Avg Prosecution
32 currently pending
Career history
715
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
48.0%
+8.0% vs TC avg
§102
18.2%
-21.8% vs TC avg
§112
23.7%
-16.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 683 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statements (IDS) submitted on 19 September 2024, 05 December 2024, and 20 October 2025 have been considered by the examiner. Claim Objections Claim 3 is objected to because of the following informalities: Line 2 appears to contain a typographical omission and is understood to read “… a third gas pipe through which a second inert gas is …” Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claims 1-17 are rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0134586 to Nakagawa et al. (“Nakagawa”). With regard to Claims 1-16, Nakagawa teaches a precursor supply system and supply methods to supply vapor deposition processes and apparatus in which films are formed on substrates (see Abstract; ¶¶ [0001]-[0002], [0161]-[0171]). Nakagawa does not expressly teach a process vessel in which a substrate is accommodated, but the reference is directed to supplying so-called “latter processes” including vapor film deposition on semiconductor substrates (see ¶¶ [0001]-[0002]). Accordingly, a process vessel in which a substrate is accommodated is deemed implicit in the disclosure of Nakagawa, and one of ordinary skill in the art would reasonably recognize as such. Nakagawa teaches an outward conduction line L2 (first gas pipe) through which process gas is supplied to a latter process, and inclusion of a flow rate measuring device 25 therewith (see FIGs. 1-2; ¶¶ [0059], [0082]-[0083], [0162], [0170]). Nakagawa teaches second and third gas pipes L1, L3 with regulators 35, 36 through which inert gases are supplied to a tank 11 (see FIGs. 1-2). The reference teaches a controllable heater 12 for the tank 11, and in-line pipe heaters for controlling temperature of supplied inert gasses (see FIGs. 1-3; ¶¶ [0272]). Nakagawa teaches a controller 50 configured to control and regulate flow rate, temperature of all facets of the precursor supply system via a detection-informed feedback loop in order to supply precursor material to downstream vapor deposition processes at target values, including flow rates and concentrations thereof (see FIGs. 1-2; ¶¶ [0031]-[0033], [0044]-[0157], [0171]-[0181], [0240]; Exemplary Embodiments). With regard to Claim 17, Nakagawa teaches computer-readable memory to facilitate storage and execution of process controls (see ¶¶ [0175], [0240]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael P Rodriguez whose telephone number is (571)270-3736. The examiner can normally be reached 9:00 - 6:00 Eastern M-F. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael Cleveland can be reached at 571-272-1418. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Michael P. Rodriguez/Primary Examiner, Art Unit 1712
Read full office action

Prosecution Timeline

Sep 19, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
73%
Grant Probability
99%
With Interview (+29.1%)
2y 8m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 683 resolved cases by this examiner. Grant probability derived from career allowance rate.

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