Prosecution Insights
Last updated: August 18, 2026
Application No. 18/890,598

TRANSMISSION DEVICE, METHOD, AND STORAGE MEDIUM

Final Rejection §103
Filed
Sep 19, 2024
Priority
Mar 22, 2022 — JP 2022-045816 +1 more
Examiner
SERRAO, RANODHI N
Art Unit
2444
Tech Center
2400 — Computer Networks
Assignee
Denso Corporation
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
1y 6m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
483 granted / 553 resolved
+29.3% vs TC avg
Strong +16% interview lift
Without
With
+15.6%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
19 currently pending
Career history
572
Total Applications
across all art units

Statute-Specific Performance

§101
17.5%
-22.5% vs TC avg
§103
31.2%
-8.8% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
12.5%
-27.5% vs TC avg
Black line = Tech Center average estimate • Based on career data from 553 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments and amendments, filed 5/19/26, with respect to the interpretation of claim 1 under 35 U.S.C. 112(f), the rejection of claim 12 under 35 U.S.C. 101, and the rejection of claims 1, 11 and 12 under 35 U.S.C. 112(b) have been fully considered and are persuasive. Therefore the interpretation and rejections have been withdrawn. Applicant’s arguments and amendments, with respect to the rejection(s) of the claim(s) under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of newly found prior art. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nakata (2010/0046520), herein after referred to as “Nakata 1,” in view of Shaffer et al. (6,707,821). As per claim 1, Nakata 1 teaches a transmission device that transmits a plurality of packets through a plurality of communication paths with load distribution, the transmission device comprising a processor and a memory storing instructions, wherein the processor executes the instructions to perform: calculating predicted delays, which are time periods required for arrival of the packets at a reception device when the packets are transmitted through the plurality of communication paths, the predicted delays being calculated based on data amounts of packets held in a holding unit, which holds the plurality of packets in order of arrival in a memory, and based on line speeds of the plurality of communication paths [Nakata 1, paragraphs 0084, 0098 and 0107]; updating at least part of sequence numbers that are applied to the packets in the order of arrival by adding a margin based on the predicted delay to the sequence number [Nakata 1, paragraphs 0013 and 0018]; selecting the communication paths that transmit the plurality of packets so that the packet in which a smaller sequence number is applied arrives earlier to the reception device [Nakata 1, paragraphs 0080-0083]; and transmitting the plurality of packets through the selected respective communication paths [Nakata 1, paragraph 0084]. But Nakata 1 fails to explicitly teach, however, Shaffer et al. in the same field of endeavor teaches a plurality of packets arriving from a higher layer [Shaffer et al., co. 4, ll. 36-59]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nakata 1 with Shaffer et al. in order to improve the regularity of voice packet transmission and lessen the average voice packet transmission delay. Claims 11-12 have similar limitations as to the rejected claims above therefore they are being rejected under the same rationale. Claim(s) 3-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nakata (2010/0046520), herein after referred to as “Nakata 1,” in view of Shaffer et al. (6,707,821) as applied to claim 1 above, and further in view of Nakata (2010/0172243), herein after referred to as “Nakata 2”. As per claim 3, Nakata 1 in view of Shaffer et al. teaches the limitations of claim 1 as above but fails to explicitly teach, however, Nakata 2 in the same field of endeavor teaches the transmission device according to claim 1, wherein the processor sets the margin based on the predicted delay regarding packets that are capable of being transmitted within an allowable delay that is a value set to balance load distribution between the plurality of communication paths [Nakata 2, paragraph 0004]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Nakata 1 and Shaffer et al. with Nakata 2 in order to enable both of optimum allocation of the load between the paths and the prevention of a delay increase due to multiplexing. As per claim 4, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein the processor sets the margin corresponding to a predicted delay difference that is a difference between a predicted delay of a packet to be transmitted through the high-latency communication path and a predicted delay of a packet to be transmitted through a low-latency communication path [Nakata 2, paragraph 0013]. As per claim 5, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein the processor sets the margin corresponding to a line speed of a low-latency communication path among the plurality of communication paths [Nakata 2, paragraph 0020]. As per claim 6, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 4, wherein the processor sets the margin corresponding to an offset obtained by multiplying the predicted delay difference by a line speed of the low-latency communication path [Nakata 2, paragraph 0059]. As per claim 7, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein the processor defines the margin by a natural number [Nakata 2, paragraph 0064]. As per claim 8, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein when data amounts of the plurality of packets are not the same, the processor defines the margin by the data amount and selects, as the packet that is later in the order of arrival, a predetermined packet in a case in which a difference between the sum of the data amounts of sequential packets, which is from the packet next to the packet selected based on the predicted delay to the predetermined packet and the data amount defined as the margin is within a predetermined range [Nakata 2, paragraphs 0028-0032]. As per claim 9, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein when two or more low-latency communication paths are present, the processor sets the sum of margins regarding the low-latency communication paths as a final margin [Nakata 2, paragraph 0055]. As per claim 10, Nakata 1-Shaffer-Nakata 2 teaches the transmission device according to claim 1, wherein the processor transmits the packets, the number of which is completely transmitted within an allowable delay set to balance load distribution between the plurality of communication paths [Nakata 2, paragraph 0064]. There are prior art made of record not relied upon but is considered pertinent to applicant's disclosure. See attached. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANODHI N SERRAO whose telephone number is (571)272-7967. The examiner can normally be reached Monday to Friday 8:00 am to 4:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, John Follansbee can be reached on (571) 272-3964. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Ranodhi N. Serrao /RANODHI SERRAO/Primary Examiner, Art Unit 2444
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Prosecution Timeline

Sep 19, 2024
Application Filed
Feb 27, 2026
Non-Final Rejection mailed — §103
May 19, 2026
Response Filed
Jun 26, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
99%
With Interview (+15.6%)
3y 5m (~1y 6m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 553 resolved cases by this examiner. Grant probability derived from career allowance rate.

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