DETAILED ACTION
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-6, 8-10, 17-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Robutel (US 2016/0087030).
Regarding claim 1, Robutel discloses a capacitor structure (Fig. 1-7), comprising: a first capacitor device structure (Fig. 1, bottom die capacitor), comprising: a first substrate (Fig. 2b, 1); and a plurality of first capacitors (Fig. 2a, 3-5), located in the first substrate (Fig. 2a); a first circuit layer (Fig. 2a, 6), located on the first capacitor device structure (Fig. 2a); and at least one second capacitor device structure (Fig. 7, second die capacitor), located on the first circuit layer (Fig. 7), wherein the second capacitor device structure comprises: a second substrate (Fig. 2a, 1); and a plurality of second capacitors (Fig. 2a, 3-5), located in the second substrate (Fig. 2a), wherein the plurality of first capacitors and the plurality of second capacitors are connected in parallel by the first circuit layer (Fig. 7 [0057]).
Regarding claim 2, Robutel further discloses: at least one second circuit layer (Fig. 2a, 6 for second die), wherein the second circuit layer is located on the second capacitor device structure (Fig. 7).
Regarding claim 3, Robutel further discloses: a third capacitor device structure (Fig. 7, 3rd die), located on the second circuit layer (Fig. 7), wherein the third capacitor device structure comprises: a first dielectric layer (Fig. 2a, 1); and a plurality of third capacitors (Fig. 2a, 3-5), located in the first dielectric layer (Fig. 2a), wherein the plurality of second capacitors and the plurality of third capacitors are connected in parallel by the second circuit layer (Fig. 7 [0057]).
Regarding claim 4, Robutel further discloses: a third circuit layer (Fig. 2a, 6 for 3rd die), wherein the third circuit layer is located on the third capacitor device structure (Fig. 7).
Regarding claim 5, Robutel further discloses that the plurality of first capacitors comprise a plurality of first electrode layers (Fig. 2a, 3), a plurality of second electrode layers (Fig. 2a, 5), and a plurality of first insulating layers (Fig. 2a, 4), the plurality of first insulating layers are located between the plurality of first electrode layers and the plurality of second electrode layers (Fig. 2a), the plurality of second capacitors comprise a plurality of third electrode layers (Fig. 2a, 3), a plurality of fourth electrode layers (Fig. 2a, 5), and a plurality of second insulating layers (Fig. 2a, 4), the plurality of second insulating layers are located between the plurality of third electrode layers and the plurality of fourth electrode layers (Fig. 2a and 7, for second die), the plurality of third capacitors comprise a plurality of fifth electrode layers (Fig. 2a, 3), a plurality of sixth electrode layers (Fig. 2a, 5), and a plurality of third insulating layers (Fig. 2a, 4), and the plurality of third insulating layers are located between the plurality of fifth electrode layers and the plurality of sixth electrode layers (Fig. 2a and 7, for 3rd die).
Regarding claim 6, Robutel further discloses that the first circuit layer comprises: a first interconnect structure (Fig. 6, top electrode +), wherein the plurality of first electrode layers and the plurality of third electrode layers are electrically connected to each other by the first interconnect structure (Fig. 7); and a second interconnect structure (Fig. 6, top electrode -), wherein the plurality of second electrode layers and the plurality of fourth electrode layers are electrically connected to each other by the second interconnect structure (Fig. 7).
Regarding claim 8, Robutel further discloses: a first bonding pad and a second bonding pad (Fig. 7, top pads on left and right), located above the third capacitor device structure and separated from each other (Fig. 7).
Regarding claim 9, Robutel further discloses that the plurality of first electrode layers, the plurality of third electrode layers, and the plurality of fifth electrode layers are electrically connected to each other and are electrically connected to the first bonding pad (Fig. 7), and the plurality of second electrode layers, the plurality of fourth electrode layers, and the plurality of sixth electrode layers are electrically connected to each other and are electrically connected to the second bonding pad (Fig. 7).
Regarding claim 10, Robutel further discloses that the plurality of first electrode layers, the plurality of third electrode layers, and the plurality of fifth electrode layers are electrically connected to each other and are electrically connected to the second bonding pad (Fig. 7, when second pad is considered left pad), and the plurality of second electrode layers, the plurality of fourth electrode layers, and the plurality of sixth electrode layers are electrically connected to each other and are electrically connected to the first bonding pad (Fig. 7, when first pad is considered right pad).
Regarding claim 17, Robutel further discloses that the at least one second capacitor device structure comprises a plurality of second capacitor device structures (Fig. 7, when they are the 2 middle dies), the plurality of second capacitor device structures are stacked on the first circuit layer (Fig. 7), the second circuit layer is located between two adjacent second capacitor device structures, and the second capacitor of the two adjacent second capacitor device structures are connected in parallel by the second circuit layer (Fig. 7).
Regarding claim 18, Robutel further discloses: a second dielectric layer (Fig. 6, bottom passivation of lower second die), located between the first substrate and the second substrate of the lowermost second capacitor device structure (Fig. 7); and a third dielectric layer (Fig. 6, bottom passivation of upper second die), located between two adjacent second substrates of the two adjacent second capacitor device structures (Fig. 7).
Regarding claim 19, Robutel further discloses that the plurality of first capacitors comprise a plurality of first electrode layers (Fig. 2a, 3), a plurality of second electrode layers (Fig. 2a, 5), and a plurality of first insulating layers (Fig. 2a, 4), the plurality of first insulating layers are located between the plurality of first electrode layers and the plurality of second electrode layers (Fig. 2a), the plurality of second capacitors comprise a plurality of third electrode layers (Fig. 2a, 3), a plurality of fourth electrode layers (Fig. 2a, 5), and a plurality of second insulating layers (Fig. 2a, 4), and the plurality of second insulating layers are located between the plurality of third electrode layers and the plurality of fourth electrode layers (Fig. 2a and 7, for second die).
Regarding claim 20, Robutel further discloses that a first interconnect structure (Fig. 6, top electrode +), wherein the plurality of first electrode layers and the plurality of third electrode layers are electrically connected to each other by the first interconnect structure (Fig. 7); and a second interconnect structure (Fig. 6, top electrode -), wherein the plurality of second electrode layers and the plurality of fourth electrode layers are electrically connected to each other by the second interconnect structure (Fig. 7).
Allowable Subject Matter
Claims 7 and 11-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Regarding claim 7, the prior art fails to teach or make obvious, alone or in combination, the limitation of “wherein the first capacitor device structure further comprises: a plurality of second dielectric layers, located between the plurality of first electrode layers and the first substrate, and the second capacitor device structure further comprises: a plurality of third dielectric layers, located between the plurality of third electrode layers and the second substrate” in combination with the other claim limitations.
Regarding claims 11-16, the prior art fails to teach or make obvious, alone or in combination, the limitation of “a second dielectric layer, located on the second capacitor device structure, the third capacitor device structure, the second circuit layer, and the third circuit layer; and a first contact and a second contact, located in the second substrate and the second dielectric layer respectively, wherein the first circuit layer, the first contact, the second circuit layer, and the second contact are electrically connected to each other” in combination with the other claim limitations.
Additional Relevant Prior Art:
Andry et al (US 2015/0221613) teaches relevant art in Fig. 1-7.
Bower et al (US 2017/0141115) teaches relevant art in Fig. 1-20.
LU et al (US 2021/0005707) teaches relevant art in Fig. 1-14.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL P MCFADDEN whose telephone number is (571)270-5649. The examiner can normally be reached M-Thur 8am-9pm PST.
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/MICHAEL P MCFADDEN/Primary Examiner, Art Unit 2847
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