CTNF 18/891,071 CTNF 86088 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 02-25 AIA Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Japan on 3/24/2022 . It is noted, however, that applicant has not filed a certified copy of the JP2022-048713 application as required by 37 CFR 1.55. On 10/28/2024 Applicant was notified that an attempt was made to electronically retrieve the priority document, however, the retrieval was unsuccessful. MPEP 2920.05(d) notes that, while the Office will attempt to retrieve the files, “Applicants are reminded that they continue to bear the ultimate responsibility for ensuring that the priority document is filed during the pendency of the application and before the patent is issued.” 07-30-03-h AIA Claim Interpretation Regarding claim 1, the claim recites that “wherein when no short-circuit failure occurs on the semiconductor switching element, the gate voltage starts to increase when the semiconductor switching element turns ON and stops the increase to reach a mirror voltage,” upon comparison with the prior art, such as that of Bachhuber (Pub. No. US 2020/0228109 A1; hereafter Bachhuber), the prior art in general uses the term “Miller voltage” to refer to the equivalent voltage in the circuit (see Bachhuber Fig. 5, V Miller ), and this seems to be a consistent term in the art. A “mirror voltage” generally appears to refer to a different type of voltage. While Applicant is allowed to be their own lexicographer, clarification is requested as to whether Applicant intends the term “mirror voltage” to be equivalent to the more common “Miller voltage.” For the purposes of this examination, the terms are going to be considered equivalent. Drawings 06-22 AIA The drawings are objected to because the circuit drawings of Figs. 1, 3, and 5 do not show any source for the gate voltage of IGBT 11. Figs. 1, 3, and 5 have a line going to the gate of IGBT 11, and Figs. 2, 4, and 6 show that a voltage source provides a gate voltage to the gate, but the figures only show the gate connected to the comparator 29, which does not supply the gate voltage. While one having ordinary skill in the art could infer that the figures are omitting a source as an implied well-known component which much be present in the invention, as presented the figures are confusing. The gate as presented in the figures does not appear to have any voltage source. In order clarify the drawings it is suggested that a source voltage for the gate be shown, making it clear that the comparator is sensing this gate voltage, and not somehow supplying the gate voltage, as the current figures would suggest . Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claim 2 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 2 recites that “the DESAT detecting circuit includes a resistor element connected to the capacitor, changing a rate of change of the DESAT voltage to be higher when switching the semiconductor switching element.” However, the term “to be higher” is a comparative term to which nothing is compared. Higher than what? The metes and bounds of the claim are therefore indefinite, because it is unclear what the rate of change needs to be higher than to meet the claimed limitation. For the purposes of this examination, the presence of the resistor inherently changes the nature of the circuit, and the rate of change of the desat voltage will inherently be higher than some value (e.g. a slope of zero), therefore the claim limitation will be construed as met as long as there is any resistor present connected to the capacitor as called for in claim 2. Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 1-3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bachhuber (Pub. No. US 2020/0228109 A1; hereafter Bachhuber) in view of Zhang et al. (Pub. No. US 2016/0124037 A1; hereafter Zhang) . Regarding claim 1, Bachhuber discloses a short-circuit detecting circuit, applied for a DESAT detecting circuit provided with a diode of which the cathode is connected to a high potential side terminal of an insulated gate type semiconductor switching element and a capacitor of which the first end is connected to an anode side of the diode and a second end is connected to a low potential side of the semiconductor switching element (see Bachhuber Fig. 4, items 201, 203, and C DESAT . Items 201 and C DESAT are both coupled to ground), detecting a short-circuit of the semiconductor element, the short-circuit detecting circuit comprising: a gate voltage terminal though which a gate voltage of the semiconductor is acquired (see Bachhuber Fig. 4, items GATE, G, and V GS ); a DESAT voltage terminal through which a desaturation voltage corresponding to a capacitor voltage of the capacitor is acquired (see Bachhuber Fig. 4, items DESAT, 196, and C DESAT ); and a determination circuit that detects, based on (i) the gate voltage exceeding a predetermined gate voltage threshold (see Bachhuber Figs. 4 and 5, items 183 and V BLANC ) and (ii) the DESAT voltage exceeding a predetermined DESAT voltage threshold, a short-circuit of the semiconductor switching element, wherein when no short-circuit failure occurs on the semiconductor switching element, the gate voltage starts to increase when the semiconductor switching element turns ON and stops the increase to reach a mirror voltage, then the gate voltage restarts to increase to become a constant voltage (see Bachhuber Figs. 4 and 5, items 180 and V miller ). Bachhuber does not disclose that the gate voltage threshold is higher than the mirror voltage of the semiconductor switching element. Bachhuber discloses using a blanking voltage as the threshold, which is lower than the Miller threshold. Zhang discloses a short circuit detection device wherein a gate voltage terminal though which a gate voltage of the semiconductor is acquired (see Chang Fig. 4, items 412, G, and VGE); a DESAT voltage terminal through which a desaturation voltage is acquired (see Zhang Fig. 4, items 420, and Vdesat); and a determination circuit that detects, based on (i) the gate voltage exceeding a predetermined gate voltage threshold (see Zhang Figs. 4 and 5, 420 and V gth ) and (ii) the DESAT voltage exceeding a predetermined DESAT voltage threshold, a short-circuit of the semiconductor switching element, wherein when no short-circuit failure occurs on the semiconductor switching element, the gate voltage starts to increase when the semiconductor switching element turns ON and stops the increase to reach a mirror voltage, then the gate voltage restarts to increase to become a constant voltage (see Zhang Figs. 4 and 5, items 420 and V DESAT ); wherein the gate voltage threshold is higher than the mirror voltage of the semiconductor switching element (see Zhang paragraph [0034] “the gate threshold voltage V gth is set to a value corresponding to slightly higher than the Miller Plateau level of the IGBT Q1”). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to use a threshold like that in Zhang as the comparison threshold instead of a lower blanking threshold like that in Bachhuber in order to provide an adaptive blanking time which is capable of having a shorter sensing period than set timers with preset blanking times which may be too long, as taught by Zhang. Regarding claim 2, Bachhuber as modified discloses the short-circuit detecting circuit according to claim 1, and Zhang further discloses that it was well known in DESAT detecting circuits to include a resistor element connected to the capacitor, changing a rate of change of the DESAT voltage to be higher when switching the semiconductor switching element (see Zhang Fig. 2B, item Rdesat). It would have been obvious to one having ordinary skill in the art at the time the invention was filed to provide the device of Bachhuber with a desat resistor like that in Zhang in order to set the circuit voltages and currents to the desired levels. Regarding claim 3, Bachhuber as modified discloses the short-circuit detecting circuit according to claim 2 further comprising a charge timing control circuit, wherein the determination circuit includes a comparator of which a logical state of an output signal changes to be H when the gate voltage exceeds the gate voltage threshold (see Bachhuber Fig. 4, item 183); and the charge timing control circuit is configured to connect between a gate of a MOSFET connected in parallel to the capacitor and an output terminal of the comparator (see Bachhuber Fig. 4, items 187-190 are between MOSFET 191 and the comparator, and the MOSFET is in parallel to capacitor C DESAT ), and supplies a logical inversion signal of an output signal of the comparator to the gate of the MOSFET (see Bachhuber Fig. 4, item 189 is a NAND gate, which provides an inverted signal in all cases except where the output of 183 is HIGH and the output of the AND gate 199 is LOW. Since there are instances when the NAND gate 189 “supplies a logical inversion signal of an output signal of the comparator to the gate of the MOSFET” the claim limitations are met, even if this is not the case for all situations.). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to NOAM S REISNER whose telephone number is (571)270-7542. The examiner can normally be reached Monday-Friday 9:00AM-5:30PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, STEPHANIE BLOSS can be reached at 571-272-3555. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /NOAM REISNER/ Primary Examiner, Art Unit 2852 5/8/2026 Application/Control Number: 18/891,071 Page 2 Art Unit: 2852 Application/Control Number: 18/891,071 Page 3 Art Unit: 2852 Application/Control Number: 18/891,071 Page 4 Art Unit: 2852 Application/Control Number: 18/891,071 Page 5 Art Unit: 2852 Application/Control Number: 18/891,071 Page 6 Art Unit: 2852 Application/Control Number: 18/891,071 Page 7 Art Unit: 2852 Application/Control Number: 18/891,071 Page 8 Art Unit: 2852
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