DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/13/2026 has been entered.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 10-12 and 21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 2023/0206855 A1).
As to claim 1, Park et al. teaches a pixel (PX in Fig. 11) comprising: a light-emitting element ([0128]: organic light-emitting diode);
a first transistor (T1 in Fig. 11) connected between a first voltage line (ELVDD line in Fig. 11) and the light-emitting element ([0128]: organic light emitting diode, Fig. 11);
a second transistor (T5 in Fig. 11) connected between the first voltage line (ELVDD line in Fig. 11) and a first terminal of the first transistor (T1 in Fig. 11); a third transistor (T6 in Fig. 11) connected between the first transistor (T1 in Fig. 11) and the light-emitting element (([0128]: organic light emitting diode, Fig. 11), a first terminal of the third transistor (T6 in Fig. 11) being connected to a second terminal of the first transistor (T1 in Fig. 11) and a second terminal of the third transistor (T6 in Fig. 11) being connected to the light-emitting element ([0128]: organic light-emitting diode; note that the claim does not recite the first terminal of the third transistor directly connected to the first transistor and the second terminal of the third transistor directly connected to the light-emitting element. All of the elements in Fig. 11 are connected to each other); and a fourth transistor (T4 in Fig. 11) connected between the light-emitting element ([0128]: organic light emitting diode, Fig. 11) and a second voltage line (VIL line in Fig. 11), wherein the pixel is configured to emit light in a plurality of emission periods (light emitting periods P2, P2’ in Fig. 6; [0112-0113]) between a plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame Abstract; [0074]; [0112-0113]: frame 1F), and the second transistor (T5 in Fig. 11) is turned off (Fig. 11 shows the gate of transistor T5 is connected to signal EM; [0129]: T5 is N-channel oxide semiconductor transistor; [0134]: period D7 in the second non-light-emitting period P1′, light-emitting control signal EM supplied as OFF voltage) and the third transistor (T6 in Fig. 11) is turned on ([0129-0130]: T6 is N-channel oxide semiconductor transistor. Transistor T6 is turned on according to a fourth scan signal EB; [0134]: period D7 in the second non-light-emitting period P1′, scan signal EB having an ON voltage is supplied, the sixth transistor T6 turned on) in even-numbered non-emission periods (even-numbered non-light emitting periods P1’ in Fig. 6) among the plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame (Abstract; [0112-0113]: frame 1F), and a gate signal provided to a gate of the second transistor (T5 in Fig. 11) and a gate signal provided to a gate of the third transistor (T6 in Fig. 11) are different from each other (Fig. 11 shows the gate of transistor T5 is connected to signal EM and the gate of transistor T6 is connected to signal EB).
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As to claim 2, Park et al. teaches the pixel of claim 1, wherein the pixel is configured to emit light in at least four emission periods ((light emitting periods P2, P2’ in Fig. 6; [0112-0113]) during the one frame ([0112-0113]: frame 1F), the first transistor (T1 in Fig. 11) is a driving transistor ([0129]: driving transistor), the second transistor (T5 in Fig. 11) is a first emission control transistor ([0109]: light-emitting control signal EM having an ON voltage turns on the fifth transistor T5), the third transistor (T6 in Fig. 11) is a second emission control transistor([0133]: transistor T6 is turned on, the pixel electrode of the organic light-emitting diode is reset), and the fourth transistor (T4 in Fig. 11) is a reset transistor ([0128]: Fig. 11, transistor T4 transmits initialization voltage VINT;[0136]: node N3 is initialized to the initialization voltage VINT).
As to claim 10, Park et al. teaches the pixel of claim 1, further comprising: a first capacitor (C1 in Fig. 11) connected between a gate of the first transistor (T1 in Fig. 11) and a node (N3 in Fig. 11) to which the first transistor (T1 in Fig. 11) and the third transistor are connected (T6 in Fig. 11); and a second capacitor (C2 in Fig. 11) connected between the first voltage line (ELVDD line in Fig. 11) and the node (N3 in Fig. 11).
As to claim 11, Park et al. teaches a display apparatus (Abstract: display) comprising: a plurality of pixels (Abstract: pixels); and a driving circuit that outputs gate signals to the plurality of pixels ([0073]: transmit light-emitting control signal EM to pixels PX; [0076]; [0131]: provide scan signal EB), wherein each of the plurality of pixels includes: a light-emitting element ([0128]: organic light-emitting diode);
a first transistor (T1 in Fig. 11) connected between a first voltage line (ELVDD line in Fig. 11) and the light-emitting element ([0128]: organic light emitting diode, Fig. 11);
a second transistor (T5 in Fig. 11) connected between the first voltage line (ELVDD line in Fig. 11) and a first terminal of the first transistor (T1 in Fig. 11); a third transistor (T6 in Fig. 11) connected between the first transistor (T1 in Fig. 11) and the light-emitting element (([0128]: organic light emitting diode, Fig. 11), a first terminal of the third transistor (T6 in Fig. 11) being connected to a second terminal of the first transistor (T1 in Fig. 11) and a second terminal of the third transistor (T6 in Fig. 11) being connected to the light-emitting element ([0128]: organic light-emitting diode; note that the claim does not recite the first terminal of the third transistor directly connected to the first transistor and the second terminal of the third transistor directly connected to the light-emitting element. All of the elements in Fig. 11 are connected to each other); and a fourth transistor (T4 in Fig. 11) connected between the light-emitting element ([0128]: organic light emitting diode, Fig. 11) and a second voltage line (VIL line in Fig. 11), wherein each of the plurality of pixels is configured to emit light in a plurality of emission periods (light emitting periods P2, P2’ in Fig. 6; [0112-0113]) between a plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame (Abstract; [0074]; [0112-0113]: frame 1F), and the driving circuit is configured to output a first gate signal of a gate-off voltage to the second transistor (Fig. 11 shows the gate of transistor T5 is connected to signal EM; [0134]: period D7 in the second non-light-emitting period P1′, light-emitting control signal EM supplied as OFF voltage) and output a second gate signal of a gate-on voltage to the third transistor ([0129-0130]: Transistor T6 is turned on according to a fourth scan signal EB; [0134]: period D7 in the second non-light-emitting period P1′, scan signal EB having an ON voltage is supplied) in even-numbered non-emission periods (even-numbered non-light emitting periods P1’ in Fig. 6) among the plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame (Abstract; [0112-0113]: frame 1F), and
a gate signal provided to a gate of the second transistor (T5 in Fig. 11) and a gate signal provided to a gate of the third transistor (T6 in Fig. 11) are different from each other (Fig. 11 shows the gate of transistor T5 is connected to signal EM and the gate of transistor T6 is connected to signal EB).
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As to claim 12, Lee et al. teaches the display apparatus of claim 11, whereinthe plurality of pixels (col. 13, lines 6-7: pixels PX) are configured to emit light in at least four emission periods (four emission EP periods in Fig. 2; col. 8, lines 37-40: emission period EP) during one frame (frame period FP in Fig. 2;col. 8, lines 37-40: emission period EP), the first transistor (T1 in Fig. 1) is a driving transistor (col. 6, line 3; driving transistor),the second transistor (T2 in Fig. 1) is a first emission control transistor (col. 6, lines 14-15: transistor T2 transfer data voltage VDAT; col. 11, lines 11-16: data voltage VDAT set such that an area of a luminance LUM in each emission period corresponds to an average luminance), the third transistor (T7 in Fig. 1) is a second emission control transistor(col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level), andthe fourth transistor (T4 in Fig. 1) is a reset transistor (col. 6, lines 34-36: transistor T4 transfer an initialization voltage VINIT to the gate node NG in response to a gate initialization signal GI).
As to claim 21, Park et al. teaches a pixel (PX in Fig. 11) comprising:
a light-emitting element ([0128]: organic light-emitting diode);
a first transistor (T1 in Fig. 11) connected between a first voltage line (ELVDD line in Fig. 11) and the light-emitting element ([0128]: organic light emitting diode, Fig. 11) ;
a second transistor (T5 in Fig. 11) connected between the first voltage line (ELVDD line in Fig. 11) and the first transistor (T1 in Fig. 11);
a third transistor (T6 in Fig. 11) connected between the first transistor (T1 in Fig. 11) and the light-emitting element ([0128]: organic light emitting diode, Fig. 11), a first terminal of the third transistor (T6 in Fig. 11) being connected to the first transistor (T1 in Fig. 11) and a second terminal of the third transistor (T6 in Fig. 11) being connected to the light-emitting element([0128]: organic light-emitting diode; note that the claim does not recite the first terminal of the third transistor directly connected to the first transistor and the second terminal of the third transistor directly connected to the light-emitting element. All of the elements in Fig. 11 are connected to each other);
a fourth transistor (T4 in Fig. 11) connected between the light-emitting element ([0128]:
organic light emitting diode, Fig. 11) and a second voltage line (VIL line in Fig. 11);
a first capacitor (C1 in Fig. 11) connected between a gate of the first transistor (T1 in Fig. 11) and a node (N3 in Fig. 11) to which the first transistor (T1 in Fig. 11) and the third transistor are connected (T6 in Fig. 11); and
a second capacitor (C2 in Fig. 11) connected between the first voltage line (ELVDD line in Fig. 11) and the node (N3 in Fig. 11), wherein:
the pixel is configured to emit light in a plurality of emission periods (light emitting periods P2, P2’ in Fig. 6; [0112-0113]) between a plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame (Abstract; [0074]; [0112-0113]: frame 1F), and
the second transistor (T5 in Fig. 11) is turned off (Fig. 11 shows the gate of transistor T5 is connected to signal EM; [0129]: T5 is N-channel oxide semiconductor transistor; [0134]: period D7 in the second non-light-emitting period P1′, light-emitting control signal EM supplied as OFF voltage) and the third transistor (T6 in Fig. 11) is turned on ([0129-0130]: T6 is N-channel oxide semiconductor transistor. Transistor T6 is turned on according to a fourth scan signal EB; [0134]: period D7 in the second non-light-emitting period P1′, scan signal EB having an ON voltage is supplied, the sixth transistor T6 turned on) in even-numbered non-emission periods (even-numbered non-light emitting periods P1’ in Fig. 6) among the plurality of non-emission periods (non-light emitting periods P1, P1’ in Fig. 6; [0112-0113]) during one frame (Abstract; [0112-0113]: frame 1F).
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Claim(s) 1-2, and 11-12 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee et al. (US 11538422 B2).
As to claim 1, Lee et al. teaches a pixel (100 in Fig. 1;[0057]: pixel 100) comprising: a light-emitting element (EL in Fig. 1;col. 5, lines 52-53: light emitting diode EL); a first transistor (T1 in Fig. 1) connected between a first voltage line (VDAT line in Fig. 1) and the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL); a second transistor (T2 in Fig. 1) connected between the first voltage line (VDAT line in Fig. 1) and a first terminal of the first transistor (T1 in Fig. 1); a third transistor (T7 in Fig. 1) connected between the first transistor (T1 in Fig. 1) and the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL), a first terminal of the third transistor (T7 in Fig. 1) being connected to a second terminal of the first transistor (T1 in Fig. 1: note that the claim does not recite “directly” connected. All of the elements in Fig. 1 are connected to each other) and a second terminal of the third transistor (T7 in Fig. 1) being connected to the light-emitting element (EL in Fig. 1;col. 5, lines 52-53: light emitting diode EL); and a fourth transistor (T4 in Fig. 1) connected between the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL) and a second voltage line (ELVDD line in Fig. 1), wherein the pixel is configured to emit light in a plurality of emission periods (EP periods in Fig. 2; col. 8, lines 37-41: emission period EP) between a plurality of non-emission periods (NEP periods in Fig. 2; col. 8, lines 37-41: non-emission period NEP) during one frame (frame period FP in Fig. 2; col. 8, lines 37-41: frame period FP), and the second transistor (T2 in Fig. 1) is turned off (col. 7, lines 19-24: transistor T2 is p-type transistor which turns off when gate writing signal GW is high in Figs. 1-2) and the third transistor (T7 in Fig. 1) is turned on (col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level) in even-numbered non-emission periods (even-numbered non-emission NEP periods (i.e. second and fourth non-emission NEP periods) in Fig. 2) among the plurality of non-emission periods (non-emission NEP periods in Fig. 2; col. 8, lines 37-41: non-emission period NEP), and a gate signal provided to a gate of the second transistor(T2 in Fig. 1) and a gate signal provided to a gate of the third transistor (T7 in Fig. 1) are different from each other (col. 6, lines 13-14: transistor T2 transfer data voltage VDAT in response to a gate writing signal GW; col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level).
As to claim 2, Lee et al. teaches the pixel of claim 1, wherein the pixel is configured to emit light in at least four emission periods (four emission EP periods in Fig. 2; col. 8, lines 37-40: emission period EP) during the one frame (frame period FP in Fig. 2;col. 8, lines 37-40: emission period EP), the first transistor (T1 in Fig. 1) is a driving transistor (col. 6, line 3; driving transistor), the second transistor (T2 in Fig. 1) is a first emission control transistor (col. 6, lines 14-15: transistor T2 transfer data voltage VDAT; col. 11, lines 11-16: data voltage VDAT set such that an area of a luminance LUM in each emission period corresponds to an average luminance), the third transistor (T7 in Fig. 1) is a second emission control transistor(col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level), and the fourth transistor (T4 in Fig. 1) is a reset transistor (col. 6, lines 34-36: transistor T4 transfer an initialization voltage VINIT to the gate node NG in response to a gate initialization signal GI).
As to claim 11, Lee et al. teaches a display apparatus (Abstract: display) comprising: a plurality of pixels (col. 13, lines 6-7: pixels PX); and a driving circuit that outputs gate signals to the plurality of pixels (col. 12, lines 46-55: scan driver 630 providing gate writing signals GW to the pixels, emission driver 640 provide emission signals EM to the pixels), wherein each of the plurality of pixels includes: a light-emitting element (EL in Fig. 1;col. 5, lines 52-53: light emitting diode EL); a first transistor (T1 in Fig. 1) connected between a first voltage line (VDAT line in Fig. 1) and the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL); a second transistor (T2 in Fig. 1) connected between the first voltage line (VDAT line in Fig. 1) and a first terminal of the first transistor (T1 in Fig. 1); a third transistor (T7 in Fig. 1) connected between the first transistor (T1 in Fig. 1) and the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL), a first terminal of the third transistor (T7 in Fig. 1) being connected to a second terminal of the first transistor (T1 in Fig. 1: note that the claim does not recite “directly” connected. All of the elements in Fig. 1 are connected to each other) and a second terminal of the third transistor (T7 in Fig. 1) being connected to the light-emitting element (EL in Fig. 1;col. 5, lines 52-53: light emitting diode EL); and a fourth transistor (T4 in Fig. 1) connected between the light-emitting element (EL in Fig. 1; col. 5, lines 52-53: light emitting diode EL) and a second voltage line (ELVDD line in Fig. 1), wherein each of the plurality of pixels is configured to emit light in a plurality of emission periods (EP periods in Fig. 2; col. 8, lines 37-41: emission period EP) between a plurality of non-emission periods (NEP periods in Fig. 2; col. 8, lines 37-41: non-emission period NEP) during one frame (frame period FP in Fig. 2; col. 8, lines 37-41: frame period FP), and the driving circuit is configured to output a first gate signal of a gate-off voltage to the second transistor (col. 7, lines 19-24: transistor T2 is p-type transistor which turns off when gate writing signal GW is high in Figs. 1-2) and output a second gate signal of a gate-on voltage to the third transistor (col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level) in even-numbered non-emission periods (even-numbered non-emission NEP periods (i.e. second and fourth non-emission NEP periods) in Fig. 2) among the plurality of non-emission periods (non-emission NEP periods in Fig. 2; col. 8, lines 37-41: non-emission period NEP), and
a gate signal provided to a gate of the second transistor (T2 in Fig. 1) and a gate signal provided to a gate of the third transistor (T7 in Fig. 1) are different from each other (col. 6, lines 13-14: transistor T2 transfer data voltage VDAT in response to a gate writing signal GW; col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level).
As to claim 12, Lee et al. teaches the display apparatus of claim 11, whereinthe pixel is configured to emit light in at least four emission periods (four emission EP periods in Fig. 2; col. 8, lines 37-40: emission period EP) during the one frame (frame period FP in Fig. 2;col. 8, lines 37-40: emission period EP), the first transistor (T1 in Fig. 1) is a driving transistor (col. 6, line 3; driving transistor), the second transistor (T2 in Fig. 1) is a first emission control transistor (col. 6, lines 14-15: transistor T2 transfer data voltage VDAT; col. 11, lines 11-16: data voltage VDAT set such that an area of a luminance LUM in each emission period corresponds to an average luminance), the third transistor (T7 in Fig. 1) is a second emission control transistor(col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level), and the fourth transistor (T4 in Fig. 1) is a reset transistor (col. 6, lines 34-36: transistor T4 transfer an initialization voltage VINIT to the gate node NG in response to a gate initialization signal GI).
Allowable Subject Matter
Claims 3-9 and 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 02/13/2026 have been fully considered but they are not persuasive. Examiner respectfully disagrees with the applicant’s argument that “Lee does not disclose nor suggest at least the following claimed feature: “a gate signal provided to a gate of the second transistor and a gate signal provided to a gate of the third transistor are different from each other”.
Lee teaches “a gate signal provided to a gate of the second transistor (T2 in Fig. 1) and a gate signal provided to a gate of the third transistor (T7 in Fig. 1) are different from each other (col. 6, lines 13-14: transistor T2 transfer data voltage VDAT in response to a gate writing signal GW; col. 7, lines 3-7: transistor T7 turned on in response to the emission signal EM having the high level),” as claimed.
The cited prior art teaches applicant’s claimed invention as noted in the office action above.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STACY KHOO whose telephone number is (571)270-3698. The examiner can normally be reached Mon-Fri 8:00 am-5:00 pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Eason can be reached at 571-270-7230. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STACY KHOO/Primary Examiner, Art Unit 2624