DETAILED ACTION
This action is in response to the application filed on 9/20/2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Regarding claim 5, the limitations “the active positive state” and “the active negative state” lack proper antecedent basis. Regarding claim 15, it’s not clear as to if the limitations “a first zero state, a second zero state, a third zero state, and a fourth zero state” in lines 7-8 are the same or different from the limitations “a first zero state, a second zero state, a third zero state, and a fourth zero state” mentioned in lines 15-16. Dependent claims 16-20 inherits the deficiencies of independent claim 15 and are therefore also rejected under 35 U.S.C. 112 (b).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-9, 12-16, and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Zou et al. (US 2023/0064783). Regarding claim 1, Zou et al. discloses (see fig. 2 and 5) a two-level DC-DC converter (114) comprising: a primary side full bridge circuit (220) including: a first leg having a first electronic switch and a second electronic switch (leg comprising S1 and S2); and a second leg having a third electronic switch and a fourth electronic switch (leg comprising S3 and S4), wherein the primary side full bridge circuit is configured to generate a first voltage (operation of 220), and wherein configurations of the first electronic switch (S1), the second electronic switch (S2), the third electronic switch (S3), and the fourth electronic switch (S4) define an operating cycle pattern for the primary side full bridge circuit (operation of S1-S4); a secondary side power stage circuit (222) including a second plurality of electronic components (see components in 222), the secondary side power stage circuit configured to generate a second voltage (output from 222); a transformer (218) coupled between the primary side full bridge circuit and the secondary side power stage circuit (connection of 218 between 220 and 222); and a control circuit (110/112) configured for: controlling an operation of the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch (operation of 110/112 controlling S1-S4) to use a first zero state, a second zero state, a third zero state, and a fourth zero state within the operating cycle pattern (see fig. 5 which shows four states per switching pattern) so as to balance a number of times the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch are used (operation of 110/112 balancing switching losses between S1-S4 using the four states within each switching pattern). Regarding claims 2, 12, and 18, Zou et al. discloses (see fig. 2 and 5) that the secondary side power stage circuit (222) includes a secondary side full bridge circuit, and wherein the two-level DC-DC converter is a dual-active bridge circuit (222 is a full bridge circuit). Regarding claims 3, 13, and 19, Zou et al. discloses (see fig. 2 and 5) that the secondary side full bridge circuit is a two-level circuit (see 222). Regarding claims 4, 14, and 20, Zou et al. discloses (see fig. 2 and 5) that the secondary side power stage circuit includes a rectifier circuit (222 is a full bridge rectifier), and wherein the two-level DC-DC converter is a phase-shifted full bridge circuit (106 is phase shifted). Regarding claim 5, as best understood, Zou et al. discloses (see fig. 2 and 5) that the control circuit (110/112) configured for controlling the operation of the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch (110/112 controlling the operation of S1-S4) to use a first zero state, a second zero state, a third zero state, and a fourth zero state within the operating cycle pattern so as to balance the number of times the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch are used (see fig. 5 showing the switching states within the switching sequences for a cycle) is configured for: controlling the operation of the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch to generate the operating cycle pattern of: the first zero state, the active positive state, the second zero state, the active negative state, the third zero state, the active positive state, the fourth zero state, and the active negative state (see fig. 5 showing the switching states within the switching sequences for a cycle). Regarding claim 8, Zou et al. discloses (see fig. 2 and 5) a method of operating a two-level DC-DC converter (114) having a primary side full bridge circuit (220) and a secondary side power stage circuit (222), the primary side full bridge circuit including a first leg having a first electronic switch and a second electronic switch (leg comprising S1/S2) and a second leg having a third electronic switch and a fourth electronic switch (leg comprising S3/S4), the method comprising: controlling the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch to define an operating cycle pattern (see operating switching sequences in fig. 5) having an active positive state, an active negative state, a first zero state, a second zero state, a third zero state, and a fourth zero state over one operating cycle for the primary side full bridge circuit (see operating states within the switching sequences of fig. 5); and using the first zero state, the second zero state, the third zero state, and the fourth zero state within the operating cycle pattern so as to balance a number of times the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch are used (operation of controller 110/112 balancing switching losses between S1-S4 using the four states within each switching pattern). Regarding claim 9, Zou et al. discloses (see fig. 2 and 5) wherien a first zero state, a second zero state, a third zero state, and a fourth zero state within the operating cycle pattern so as to balance the number of times the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch are used (see fig. 5 showing the switching states within the switching sequences for a cycle) includes: generating the operating cycle pattern of: the first zero state, the active positive state, the second zero state, the active negative state, the third zero state, the active positive state, the fourth zero state, and the active negative state (see fig. 5 showing the switching states within the switching sequences for a cycle). Regarding claim 15, as best understood, Zou et al. discloses (see fig. 2 and 5) a control circuit for a two-level DC-DC converter, the two-level DC-DC converter (114) comprising: a primary side full bridge circuit (220) including: a first leg having a first electronic switch and a second electronic switch (leg comprising S1 and S2); and a second leg having a third electronic switch and a fourth electronic switch (leg comprising S3 and S4), wherein the primary side full bridge circuit is configured to generate a first voltage (operation of 220), and wherein configurations of the first electronic switch (S1), the second electronic switch (S2), the third electronic switch (S3), and the fourth electronic switch (S4) define an operating cycle pattern (see operating switching sequences in fig. 5) having an active positive state, an active negative state, a first zero state, a second zero state, a third zero state, and a fourth zero state over one operating cycle for the primary side full bridge circuit (see operating states within the switching sequences of fig. 5), the two-level DC-DC converter further including a secondary side power stage circuit (222) including a second plurality of electronic components (see components in 222), the secondary side power stage circuit configured to generate a second voltage (output from 222); a transformer (218) coupled between the primary side full bridge circuit and the secondary side power stage circuit (connection of 218 between 220 and 222); a PI controller and a phase shift angle circuit (110/112) configured for: controlling an operation of the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch (operation of 110/112 controlling S1-S4) to use a first zero state, a second zero state, a third zero state, and a fourth zero state within the operating cycle pattern (see fig. 5 which shows four states per switching pattern) so as to balance a number of times the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch are used (operation of 110/112 balancing switching losses between S1-S4 using the four states within each switching pattern). Regarding claim 16, as best understood, Zou et al. discloses (see fig. 2 and 5) that the PI controller and the phase shift angle circuit (110/112) are configured for: controlling the operation of the first electronic switch, the second electronic switch, the third electronic switch, and the fourth electronic switch to generate the operating cycle pattern of: the first zero state, the active positive state, the second zero state, the active negative state, the third zero state, the active positive state, the fourth zero state, and the active negative state (see fig. 5 showing the switching states within the switching sequences for a cycle).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 7, 11, and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Zou et al. (US 2023/0064783) in view of Mao et al. (US Patent 12427874). Regarding claims 7 and 11, Zou et al. does not disclose that the control circuit is configured for: adjusting, during either the first zero state or second zero state, a phase angle between an electronic switch of the first leg and an electronic switch of the second leg. Mao et al. discloses (see fig. 1) a control circuit (201) is configured for: adjusting, during either a first zero state or second zero state (an operating state of H1), a phase angle between an electronic switch of a first leg (Q1/Q2) and an electronic switch of the second leg (Q3/Q4) (see column 16 lines 5-10). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zou et al. to include the features of Mao et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies. Regarding claim 17, as best understood, Zou et al. does not disclose that the PI controller and the phase shift angle circuit are configured for: adjusting, during either the first zero state or second zero state, a phase angle between an electronic switch of the first leg and an electronic switch of the second leg. Mao et al. discloses (see fig. 1) a control circuit (201) is configured for: adjusting, during either a first zero state or second zero state (an operating state of H1), a phase angle between an electronic switch of a first leg (Q1/Q2) and an electronic switch of the second leg (Q3/Q4) (see column 16 lines 5-10). Therefore it would have been obvious to one having ordinary skill in the art at the time the invention was filed to modify the converter of Zou et al. to include the features of Mao et al. because it provides for a transient control means to prevent unwanted fluctuations in operation, thus increasing operational efficiencies.
Allowable Subject Matter
Claims 6 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Tschirhart et al. (US Patent 10218278) discloses an isolated DC-DC voltage converter. Harrison (US Patent 9866144) discloses a three-port converter with dual independent MPPT modes. Rehlaender et al. (US Patent 12119752) discloses an alternating asymmetrical phase-shift modulation control.
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/JEFFREY A GBLENDE/Primary Examiner, Art Unit 2838
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