DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Sakui et al. (US 2024/0206150, hereinafter “Sakui”).
Regarding claim 1, Sakui (Fig. 2D) shows an operating method of a memory device, the method comprising:
during a first time period (T11-T12) in a write operation, pre-charging a bit line (BL0) connected to a memory cell with a ground voltage (Vss);
during a second time period (T12--T14) in the write operation, applying a word line driving voltage (V11) to a word line (WL0) corresponding to the bit line;
in the second time period, applying a plate line (PL0) driving voltage (V12) to a plate line connected to the memory cell; and
in the second time period, maintaining a voltage applied to the bit line at the ground voltage.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4, 5, 8, 10 and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Dokania et al. (US 11,482,270, hereinafter “Dokania”).
Regarding claim 1, Dokania (Fig. 2E, Write 0) shows an operating method of a memory device, the method comprising:
during a first time period (t1-t2) in a write operation, pre-charging a bit line (BLx) connected to a memory cell (Fig. 2A, 2011,1) with a ground voltage (Vss);
during a second time period (t2-t3) in the write operation, applying a word line driving voltage (Vdd+Vboost) to a word line (WL1) corresponding to the bit line;
in the second time period, applying a plate line (PLx) driving voltage (Vdd) to a plate line connected to the memory cell; and
in the second time period, maintaining a voltage applied to the bit line at the ground voltage.
Regarding claim 4, Dokania (Fig. 2E) shows the operating method of claim 1, further comprising:
during a third time period (after t4) in the write operation, applying the ground voltage to the word line;
in the third time period, applying the ground voltage to the plate line; and
in the third time period, maintaining a voltage applied to the bit line at the ground voltage.
Regarding claim 5, Dokania (Fig. 2F) shows the operating method of claim 1, further comprising:
during a fourth time period (t0-12) in a read operation, pre-charging the bit line (BLx) with the ground voltage;
during a fifth time period (t2-t5) in the read operation, reading data stored in the memory cell by performing a charge sharing operation; and
during a sixth time period (t6-t7) in the read operation, rewriting the data to the memory cell by applying the plate line driving voltage (Vdd) to the plate line.
Regarding claim 8, Dokania (Fig. 2F) shows the operating method of claim 5, wherein rewriting of the data to the memory cell comprises:
in the sixth time period (t6-t7), applying a positive first plate line driving voltage (VDD) to the plate line during rewriting of first data (Write 0); and
in the sixth time period, applying the ground voltage to the plate line during rewriting of second data (write 1).
Regarding claim 10, Dokania (Fig. 10D) shows an operating method of a memory device, the method comprising:
during a first time period (t0-t2) in a read operation, applying a ground voltage (0V) to a first plate line (PL0) connected to a first memory cell and a second plate line (PL1) connected to a second memory cell (Fig. 10A);
in the first time period, applying the ground voltage to a bit line (BL0) commonly connected to the first memory cell and the second memory cell;
during a second time period (t2-t4) in the read operation, reading data stored in one of the first memory cell and the second memory cell by performing a charge sharing operation;
during a third time period (t2-t4) in the read operation, applying a first plate line driving voltage (VDD) to a plate line (PL0) corresponding to a memory cell storing first data (Read1) among the first and second memory cells; and
in the third time period, applying a second plate line driving voltage to a plate line (PL1) corresponding to a memory cell storing second data (Read0) among the first and second memory cells.
Regarding claim 14, Dokania shows (Fig. 10D) shows the operating method of claim 10, further comprising, in the third time period (t5-t6), applying the ground voltage to the bit line.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Sakui et al. in view of Carmen (CN 109155140 A).
Claims 2 and 3 differ from Dokania in reciting that applying of the plate line driving voltage to the plate line comprises: applying a positive first plate line driving voltage to the plate line during writing of first data; and applying a negative second plate line driving voltage to the plate line during writing of second data. However, Carmen discloses the use of a positive voltage applied to the plate line and a negative voltage to the plate line during writing logic 0 and 1 (In one example, the word line 110-a to activate the selection component 220, so that the capacitor 205 electrically connected to digit lines 115-a. can (outer other method) by using plate line 230 control board 210 voltage or 115-a using digital line control unit is voltage of 215 across the capacitor 205 voltage to write logic 0, the plate 210 is high, then a positive voltage is applied, and it can make the unit bottom 215 is low, namely by connecting to ground (nearly ground), or applying a negative voltage to the plate 210. performing a reverse process to write logic 1). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use a positive voltage applied to the plate line and a negative voltage to the plate line during writing logic 0 and logic 1.
It would have been obvious to one having ordinary skill in the art to recognize that the magnitude of the first plate line driving voltage is equal to the second plate line driving voltage because of opposite logic states of data.
Claims 2, 3, 6, 7, 9, 11, 12 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Dokania in view of Carmen.
Claims 2, 3, 6, 11, 12 and 13 differ from Dokania in reciting that applying of the plate line driving voltage to the plate line comprises: applying a positive first plate line driving voltage to the plate line during writing of first data; and applying a negative second plate line driving voltage to the plate line during writing of second data. However, Carmen discloses the use of a positive voltage applied to the plate line and a negative voltage to the plate line during writing logic 0 and 1 (In one example, the word line 110-a to activate the selection component 220, so that the capacitor 205 electrically connected to digit lines 115-a. can (outer other method) by using plate line 230 control board 210 voltage or 115-a using digital line control unit is voltage of 215 across the capacitor 205 voltage to write logic 0, the plate 210 is high, then a positive voltage is applied, and it can make the unit bottom 215 is low, namely by connecting to ground (nearly ground), or applying a negative voltage to the plate 210. performing a reverse process to write logic 1). It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to use a positive voltage applied to the plate line and a negative voltage to the plate line during writing logic 0 and logic 1.
It would have been obvious to one having ordinary skill in the art to recognize that the magnitude of the first plate line driving voltage is equal to the second plate line driving voltage because of opposite logic states of data.
Regarding claim 7, Donakia (Fig. 2F) shows tthe operating method of claim 6, wherein rewriting of the data to the memory cell further comprises, in the sixth time period (t6-t7), applying the ground voltage to the bit line (Write 1).
Regarding claim 9, Dokania (Fig. 2F) shows the operating method of claim 6, wherein rewriting of the data to the memory cell comprises, in a seventh time period (>t8), applying the ground voltage to the word line, the plate line, and the bit line.
Allowable Subject Matter
Claims 15-20 are allowed.
Regarding claim 15, the prior art made of record and considered pertinent to the applicant's disclosure does not teach the claimed limitation of “a second plate line decoder connected to the second layer; a common bit line connected to the first layer and the second layer; and a word line decoder connected to the first layer and the second layer, wherein, during a write operation on the memory cell array, a voltage applied to the common bit line is maintained at a ground voltage.” in combination with the other limitations thereof as is recited in the claim. Claims 16-20 depend on claim 15.
Conclusion
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/HUAN HOANG/Primary Examiner, Art Unit 2827