DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 2, 9, 12, 13, and 17-20 have been amended.
Claims 1-20 have been examined.
The § 112 rejections in the previous Office Action have been addressed and are withdrawn.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, and 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2016/0092230 by Chen et al. (hereinafter referred to as “Chen”)in view of US Publication No. 2012/0124344 by Jarvis (hereinafter referred to as “Jarvis”).
Regarding claims 1, 12, and 17, taking claim 1 as representative, Chen discloses:
a branch predictor unit (BPU), comprising (Chen discloses, at Figure 1 and related description, a system that performs branch prediction, the system including a branch history table, branch target address cache (BTAC), loop predictor, and loop buffer, which discloses a branch predictor unit.):
a loop predictor configured to predict a repeatedly looping behavior before the repeatedly looping behavior occurs (Chen discloses, at Figure 1 and related description, the loop predictor predicts the loop exit, which discloses, predict a repeatedly looping behavior before the repeatedly looping behavior occurs.);
…detect the repeatedly looping behavior which is currently occurring by detecting a branch that is potentially part of a loop and checking whether one or more next instances of the branch have …at least a threshold number of branches …and branch history (Chen discloses, at Figure 3 and related description, the loop predictor detects a backward taken branch, and a count exceeding a threshold. See, e.g., ¶¶ [0033]-[0036]. Chen also discloses, at ¶ [0019], branch history.); and
a loop buffer, configured to store representations of a plurality of looping operations corresponding to the repeatedly looping behavior as a read-only circular loop without removing the looping operations from the loop buffer (Chen discloses, at Figure 1 and related description, a loop buffer from which loop instructions are repeatedly read without being removed, which discloses a loop buffer, configured to store representations of a plurality of looping operations corresponding to the repeatedly looping behavior as a read-only circular loop without removing the looping operations from the loop buffer.).
Chen does not explicitly disclose that the aforementioned detecting is performed by a separate component referred to as a loop detector and that the aforementioned checking is based on previously recorded branch history.
However, Chen discloses that both the claimed predicting and the claimed detecting are performed by the loop predictor. Chen’s claimed loop predictor is interpreted as disclosing both the claimed loop predictor and loop detector because whether to implement two functions using a single element, as in Chen, or in two elements, as claimed, is an obvious design choice based on well-known tradeoffs such as power and complexity.
Also, in the same field of endeavor (e.g., loops) Jarvis discloses:
using branch history to detect loops (Jarvis discloses, at ¶ [0020], using branch history to detect loops.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include Jarvis’s use of branch history because doing so uses information that is commonly accessible to simply perform the desired task and enable reduction in power consumption. See Jarvis, ¶ [0014].
Regarding claims 2, 13, and 18, taking claim 2 as representative, Chen discloses the elements of claim 1, as discussed above. Chen also discloses:
determine that the loop has a length suitable for storage in the loop buffer (Chen discloses, at Figure 1 and related description, determining whether the loop fits in the loop buffer, which discloses determine that the loop has a length suitable for storage in the loop buffer.).
Regarding claims 3, 14, and 19, taking claim 3 as representative, Chen discloses the elements of claim 1, as discussed above. Chen also discloses:
the repeatedly looping behavior is defined by a plurality of repeatedly looping executions, wherein the loop predictor is further configured to: determine whether the repeatedly looping executions have a duration of looping behavior longer than a threshold duration (Chen discloses, at Figure 3 and related description, determining whether the counter is sufficiently large, which discloses the repeatedly looping behavior is defined by a plurality of repeatedly looping executions, wherein the loop predictor is further configured to: determine whether the repeatedly looping executions have a duration of looping behavior longer than a threshold duration.);
track a duration of each instance of the repeatedly looping executions (Chen discloses, at Figure 3 and related description, determining whether the counter is sufficiently large for a sufficient number of instances of the loop, which discloses track a duration of each instance of the repeatedly looping executions.);
record a branch history corresponding to a loop entrance of the repeatedly looping executions that have a duration of looping behavior longer than the threshold duration (Chen discloses, at Figure 3 and related description, creating an entry when the count criteria are met, which discloses, record a branch history corresponding to a loop entrance of the repeatedly looping executions that have a duration of looping behavior longer than the threshold duration.); and
count a number of repeatedly looping executions that have a duration of looping behavior longer than the threshold duration (Chen discloses, at Figure 3 and related description, creating an entry when the count criteria are met, which discloses, count a number of repeatedly looping executions that have a duration of looping behavior longer than the threshold duration.).
Regarding claims 4, 15, and 20, taking claim 4 as representative, Chen discloses the elements of claim 3, as discussed above. Chen also discloses:
the loop predictor is further configured to train a loop mode prediction table having a plurality of entries that are used to determine whether to enter a loop mode based at least in part on the branch history and the number of the repeatedly looping executions (Chen discloses, at Figure 3 and related description, creating an entry in a trained loop count table when the count criteria are met, which discloses, the loop predictor is further configured to train a loop mode prediction table having a plurality of entries that are used to determine whether to enter a loop mode based at least in part on the branch history and the number of the repeatedly looping executions.).
Regarding claims 5 and 16, taking claim 5 as representative, Chen discloses the elements of claim 4, as discussed above. Chen also discloses:
the loop predictor is further configured to enter the loop mode based on a determination that the branch history of a current branch matches at least one of the entries in the loop mode prediction table (Chen discloses, at Figures 5A and 5B and related description, entering loop buffer mode based on finding an entry in the trained loop counter table, which discloses the loop predictor is further configured to enter the loop mode based on a determination that the branch history of a current branch matches at least one of the entries in the loop mode prediction table.).
Regarding claim 6, Chen discloses the elements of claim 5, as discussed above. Chen also discloses:
the loop buffer is further configured to exit the loop mode upon receiving a flush (Chen discloses, at Figure 3 and related description, causing the fetch unit to begin fetching in response to a flush, which discloses the loop buffer is further configured to exit the loop mode upon receiving a flush.).
Regarding claim 7, Chen discloses the elements of claim 6, as discussed above. Chen also discloses:
a branch misprediction causes the flush (Chen discloses, at Figure 3 and related description, a branch misprediction causes a flush.).
Regarding claim 9, Chen discloses the elements of claim 1, as discussed above. Chen also discloses:
determine whether a first branch tracked by the loop detector having a first branch program counter (PC) is not detected again with a branch history that matches a prior instance of an operation having a sufficient branch history depth within a period of time or a number of predictions (Chen discloses, at Figure 3 and related description, determining whether a detected branch meets loop branch criteria, which discloses determine whether a first branch tracked by the loop detector having a first branch program counter (PC) is not detected again with a branch history that matches a prior instance of an operation having a sufficient branch history depth within a period of time or a number of predictions.);
stop tracking the first branch based on a determination that the first branch tracked by the loop detector having the first branch PC is not detected again with a branch history that matches the prior instance to the sufficient … depth (Chen discloses, at Figure 3 and related description, the method ends, which discloses stop tracking the first branch based on a determination that the first branch tracked by the loop detector having the first branch PC is not detected again with a branch history that matches the prior instance to a sufficient depth.); and
start tracking a second branch having a second branch PC (Chen discloses, at Figure 3 and related description, determining whether a detected branch meets loop branch criteria, which discloses start tracking a second branch having a second branch PC.).
Chen does not explicitly disclose that the aforementioned checking is based on branch history.
However, in the same field of endeavor (e.g., loops) Jarvis discloses:
using branch history to detect loops (Jarvis discloses, at ¶ [0020], using branch history to detect loops.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include Jarvis’s use of branch history because doing so uses information that is commonly accessible to simply perform the desired task and enable reduction in power consumption. See Jarvis, ¶ [0014].
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chen in view of Jarvis in view of US Publication No. 2024/0394064 by Tran (hereinafter referred to as “Tran”).
Regarding claim 8, Chen discloses the elements of claim 3, as discussed above. Chen also discloses:
…looping operations that have a loop duration shorter than a threshold duration are installed in the loop buffer (Chen discloses, at Figure 1 and related description, storing loop instructions in a loop buffer, which discloses, looping operations that have a loop duration shorter than a threshold duration are installed in the loop buffer.).
Chen does not explicitly disclose a plurality of copies of aforementioned looping operations.
However, in the same field of endeavor (e.g., loops) Tran discloses:
storing multiple copies of instructions in a loop buffer (Tran discloses, at Figure 5 and related description, loop unrolling, which discloses storing multiple copies of instructions in a loop buffer.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include storing multiple copies of loop operations, as disclosed by Tran, in order to improve performance by increasing parallelism. See Tran, ¶ [0041].
Claims 10 and 11 are rejected under 35 U.S.C. 103 as being unpatentable Chen in view of Jarvis in view of US Publication No. 2015/0301832 by Zhang et al. (hereinafter referred to as “Zhang”).
Regarding claim 10, Chen discloses the elements of claim 1, as discussed above. Chen also discloses:
determine a number of branch mispredictions (Chen discloses, at Figure 1 and related description, detecting a misprediction, which discloses determine a number of branch mispredictions.).
Tran does not explicitly disclose disable a loop prediction or a loop detection based on the number of branch mispredictions.
However, in the same field of endeavor (e.g., prediction) Zhang discloses:
disabling prediction based on mispredictions (Zhang discloses, at Figure 9 and related description, disabling prediction based on a misprediction rate.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include selectively disabling prediction, as disclosed by Zhang, in order to improve performance by reducing power consumption due to recovering from mispredictions. See Zhang, ¶ [0025].
Regarding claim 11, Chen discloses the elements of claim 10, as discussed above. Chen does not explicitly disclose the loop prediction or the loop detection is disabled for a number of cycles or a number of predictions.
However, in the same field of endeavor (e.g., prediction) Zhang discloses:
disabling prediction based on mispredictions (Zhang discloses, at Figure 9 and related description, disabling prediction based on a misprediction rate, which discloses the loop prediction or the loop detection is disabled for a number of cycles or a number of predictions.).
It would have been obvious to a person having ordinary skill in the art before the effective filing date of the claimed invention to modify Chen to include selectively disabling prediction, as disclosed by Zhang, in order to improve performance by reducing power consumption due to recovering from mispredictions. See Zhang, ¶ [0025].
Response to Arguments
On page 8 of the response filed August 28, 2026 (“response”), the Applicant argues, “The Office pointed to Chen's disclosure of determining whether a branch was taken a threshold number of times in order to qualify the branch as a loop branch to allegedly meet this limitation. Office Action at 3-4. The Applicant respectfully disagrees. Chen simply discloses a simple loop counter that tracks the total number of times a single branch is taken. In contrast, claim 1 recites "a branch history" (which is a sequential history of taken/not-taken outcomes across a plurality of branches, rather than just a count for a single branch) and checks whether the branch history of one or more subsequent instances matches the previously recorded branch history to a certain depth (i.e., a threshold number of branches). As described in the specification (see, e.g., paragraphs [0032]-[0033]), this allows the loop detector to recognize repeatedly looping behavior by determining that at least a threshold number of branches' worth of branch history match between two consecutive samples taken when predicting the same branch. This branch history matching mechanism allows for the detection of significantly more complex loop behaviors and is structurally and functionally distinct from Chen's simple loop counter.”
These remarks have been fully considered and, in light of the claim amendments presented in the response, are deemed persuasive. Please see above for new grounds of rejection of the amended claims.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure.
US 20040003202 by Ukai discloses detecting a loop using branch history.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHAWN DOMAN whose telephone number is (571)270-5677. The examiner can normally be reached on Monday through Friday 8:30am-6pm Eastern Time.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on 571-270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SHAWN DOMAN/
Primary Examiner, Art Unit 2183
