Listed by the USPTO as DOMAN, SHAWN
Tech Center 2100 • Art Units: 2182 2183
This examiner grants 65% of resolved cases
DOMAN, SHAWN works in tech center 2100 and art unit 2182. The profile contains 288 resolved cases, a 64.9% allowance rate, and a median of 1102 days to allowance. The 25.9% interview lift shows a meaningful association between interviews and allowance outcomes in this docket.
The leading companies are Intel Corporation, Texas Instruments Incorporated, and Advanced Micro Devices Inc. The leading firms are Adams Intellex, PLC, Greenberg Traurig, LLP - AMD, Inc., and HSML P.C. Applicants can use the profile to plan examiner engagement while maintaining a clear written record addressing claim scope and cited art.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 17686404 | SYSTEMS, METHODS, AND APPARATUS FOR COORDINATING COMPUTATION SYSTEMS | Non-Final OA | Samsung Electronics Co., Ltd. |
| 19097503 | Operation Fusion for Instructions Bridging Execution Unit Types | Non-Final OA | Apple Inc. |
| 18350907 | Combining Multiple Tensors into a Single Tensor Using Multiple Processors | Non-Final OA | Huawei Technologies Co., Ltd. |
| 18210202 | PERFORMING CONCURRENT OPERATIONS IN A PROCESSING ELEMENT | Final Rejection | Amazon Technologies, Inc. |
| 18761887 | MEMORY PREFETCH MECHANISM BASED ON INSTRUCTION SETS | Final Rejection | QUALCOMM Incorporated |
| 18594899 | FETCHING BEYOND PREDICTED-TAKEN BRANCH INSTRUCTIONS IN FETCH BUNDLES OF PROCESSOR-BASED DEVICES | Final Rejection | QUALCOMM Incorporated |
| 18091599 | PREFIX EXTENSIONS FOR EXTENDED GENERAL PURPOSE REGISTERS WITH OPTIMIZATION FEATURES FOR NON-DESTRUCTIVE DESTINATIONS AND FLAGS SUPPRESSION | Final Rejection | INTEL CORPORATION |
| 18090749 | OPTIMIZING CONCURRENT EXECUTION USING NETWORKED PROCESSING UNITS | Final Rejection | Intel Corporation |
| 17712139 | VARIABLE-LENGTH INSTRUCTION STEERING TO INSTRUCTION DECODE CLUSTERS | Final Rejection | Intel Corporation |
| 18414842 | Deep Learning Computation with Heterogeneous Accelerators | Final Rejection | Micron Technology, Inc. |
| 19274117 | CONDITIONAL BRANCH INSTRUCTIONS | Non-Final OA | Texas Instruments Incorporated |
| 19256267 | DATA PROCESSING APPARATUS HAVING STREAMING ENGINE WITH READ AND READ/ADVANCE OPERAND CODING | Non-Final OA | TEXAS INSTRUMENTS INCORPORATED |
| 18604043 | CONDITIONAL BRANCH INSTRUCTIONS FOR AGGREGATING CONDITIONAL BRANCH OPERATIONS | Final Rejection | TEXAS INSTRUMENTS INCORPORATED |
| 18790951 | INSTRUCTION EXECUTION USING EXPANDED REGISTER CONTENTS | Final Rejection | INTERNATIONAL BUSINESS MACHINES CORPORATION |
| 19224400 | GENERALIZED ACCELERATION OF MATRIX MULTIPLY ACCUMULATE OPERATIONS | Non-Final OA | NVIDIA Corporation |
| 18325806 | CATEGORIZED MEMORY OPERATIONS FOR SELECTIVE MEMORY FLUSHING | Final Rejection | NVIDIA CORPORATION |
| 19089853 | TASK EXECUTION METHOD FOR LARGE MODEL, ELECTRONIC DEVICE, AND STORAGE MEDIUM | Final Rejection | Beijing Baidu Netcom Science Technology Co., Ltd. |
| 19096299 | MEMORY DEPENDENCE PREDICTION | Final Rejection | Advanced Micro Devices, Inc. |
| 18475507 | SYSTEMS AND METHODS FOR RESYNCHRONIZATION AT EXECUTION TIME | Non-Final OA | Advanced Micro Devices, Inc. |
| 18475918 | METHOD AND APPARATUS FOR ENABLING MIMD-LIKE EXECUTION FLOW ON SIMD PROCESSING ARRAY SYSTEMS | Non-Final OA | Advanced Micro Devices, Inc. |
| 19053495 | COMPILER GENERATED HYPERBLOCKS IN A PARALLEL ARCHITECTURE WITH COMPUTE SLICES | Non-Final OA | Ascenium, Inc. |
| 17551276 | HIGHLY PARALLEL PROCESSING ARCHITECTURE USING DUAL BRANCH EXECUTION | Non-Final OA | Ascenium, Inc. |
| 18169007 | NEURAL NETWORK ACCELERATOR ARCHITECTURE BASED ON CUSTOM INSTRUCTION ON FPGA | Final Rejection | EFINIX, INC. |
IP Author analyzes examiner patterns and generates tailored response strategies with the highest chance of allowance.
Build Your Strategy64.9% of resolved applications examined by Shawn Doman were allowed (288 resolved cases), compared with 71.9% across Art Unit 2182 over the last five years.
This examiner's interview lift is +25.9 percentage points: the difference in allowance rate between resolved applications that had an examiner interview and those that did not.
Applications allowed by Shawn Doman took 1,102 days on average from filing to allowance.
Shawn Doman examines applications in Art Unit 2182 in Tech Center 2100 (Computing & Software).
